Semiconductor device including a self-formed barrier metal layer
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsShih-Kang Fu, Hsien-Chang Wu, Ming-Han Lee, Shau-Lin Shue
Life of this patent
Estimating the term…
Abstract
A semiconductor device includes a substrate, an interconnect layer disposed over the substrate, a metal line formed in the interconnect layer, a dielectric layer disposed on the interconnect layer, and a via contact formed in the dielectric layer and electrically connected to the metal line. One of the via contact and the metal line includes a first metal material and a barrier metal layer disposed on the first metal material. The first metal material includes an alloy which is a mixture of two metal elements. The barrier metal layer includes one of the two metal elements.
Claims20
A semiconductor device comprising:
- a substrate;
- an interconnect layer disposed over the substrate;
- a metal line formed in the interconnect layer;
- a dielectric layer disposed on the interconnect layer;
- and
- a via contact formed in the dielectric layer and electrically connected to the metal line, one of the via contact and the metal line including a first metal material and a barrier metal layer disposed on the first metal material, the first metal material including an alloy which is a mixture of two metal elements, the barrier metal layer including one of the two metal elements,
- wherein the semiconductor device further includes a first metal oxide layer that is disposed between the dielectric layer and the barrier metal layer of the metal line, and that is penetrated by the via contact, and
- wherein a bottom surface of the first metal oxide layer is lower than a bottom surface of the dielectric layer.
A semiconductor device comprising:
- a substrate;
- an interconnect layer disposed over the substrate;
- a metal line formed in the interconnect layer;
- a dielectric layer disposed on the interconnect layer;
- and
- a via contact formed in the dielectric layer and electrically connected to the metal line, one of the via contact and the metal line including a hybrid metal structure and a metal layer,
- wherein the hybrid metal structure includes a first metal material located at lateral and bottom regions of the hybrid metal structure, and including an alloy which is a mixture of two metal elements, and
- a second metal material located at a central region of the hybrid metal structure, and being different from the first metal material, wherein the metal layer is disposed on the first metal material of the hybrid metal structure of the metal line and laterally covers the second metal material, and
- wherein a side surface of the second metal material has a direct interface with each of the first metal material and the metal layer.
A semiconductor device comprising:
- a substrate;
- an interconnect layer disposed over the substrate;
- a metal line formed in the interconnect layer;
- a metal-containing etch stop layer disposed on the interconnect layer;
- a non-metallic etch stop layer disposed on and interfacing a top surface of the metal-containing etch stop layer;
- a dielectric layer disposed on the non-metallic etch stop layer opposite to the metal-containing etch stop layer;
- and
- a via contact formed in the dielectric layer and electrically connected to the metal line, one of the via contact and the metal line including a first metal material and a barrier metal layer disposed on the first metal material and being in contact with the metal-containing etch stop layer, the first metal material including an alloy which is a mixture of two metal elements, the barrier metal layer including one of the two metal elements.
Dependencies are inferred from the claim text.