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US 12,672,480 B2Granted
Double-gate carbon nanotube transistor
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsJin Cai, Sheng-Kai Su
Life of this patent
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Abstract
A method includes depositing a dielectric layer over a substrate, forming carbon nanotubes on the dielectric layer, forming a dummy gate stack on the carbon nanotubes, forming gate spacers on opposing sides of the dummy gate stack, and removing the dummy gate stack to form a trench between the gate spacers. The carbon nanotubes are exposed to the trench. The method further includes etching a portion of the dielectric layer underlying the carbon nanotubes, with the carbon nanotubes being suspended, forming a replacement gate dielectric surrounding the carbon nanotubes, and forming a gate electrode surrounding the replacement gate dielectric.
Claims20
A device comprising:
- a dielectric isolation layer;
- a plurality of carbon nanotubes, each comprising a first portion over and contacting the dielectric isolation layer, wherein each of the plurality of carbon nanotubes comprises a bottom surface in physical contact with the dielectric isolation layer;
- a gate stack comprising:
- a gate dielectric encircling the plurality of carbon nanotubes;
- and
- a gate electrode encircling the gate dielectric;
- a gate spacer on a sidewall of the gate stack, wherein a lower portion of the gate stack is overlapped by the gate spacer;
- a contact etch stop layer on a sidewall of the gate spacer, wherein the contact etch stop layer is further over and contacting second portions of the plurality of carbon nanotubes;
- an inter-layer dielectric over the contact etch stop layer;
- and
- a source/drain contact plug electrically connected to the plurality of carbon nanotubes, wherein the source/drain contact plug comprises a metal, and contacts a top surface and opposing edge-surfaces of each of the plurality of carbon nanotubes.
8 more elements
A device comprising:
- a substrate;
- a dielectric layer over the substrate;
- a plurality of carbon nanotubes over and contacting a first portion and a second portion of the dielectric layer;
- a gate stack extending between the first portion and the second portion of the dielectric layer, wherein the gate stack comprises:
- a gate dielectric encircling portions of the plurality of carbon nanotubes, wherein the portions of the plurality of carbon nanotubes are between the first portion and the second portion of the dielectric layer;
- and
- a gate electrode surrounding a combined region of the plurality of carbon nanotubes and the gate dielectric, wherein the gate electrode comprises an upper portion overlapping the combined region, and a lower portion overlapped by the combined region, and the lower portion forms an interface with the dielectric layer, and wherein from a bottommost part of the lower portion to a topmost part of the lower portion, the interface is continuously rounded;
- a contact etch stop layer comprising a portion over and contacting the plurality of carbon nanotubes;
- and
- an inter-layer dielectric over the contact etch stop layer.
7 more elements
A device comprising:
- a substrate comprising a top surface;
- a plurality of carbon nanotubes substantially parallel to and spaced apart from each other;
- a gate stack, wherein the plurality of carbon nanotubes are encircled by the gate stack, the gate stack comprising:
- a gate dielectric comprising a first portion directly over the plurality of carbon nanotubes, and a second portion directly under the plurality of carbon nanotubes;
- and
- a gate electrode comprising a third portion over the first portion of the gate dielectric, and a fourth portion under the second portion of the gate dielectric, wherein all of the plurality of carbon nanotubes are substantially aligned to a same plane that is over and parallel to the top surface of the substrate;
- a gate spacer on a sidewall of the gate stack, wherein the first portion of the gate dielectric and the third portion of the gate electrode extend higher than a bottom surface of the gate spacer, and the second portion of the gate dielectric and the fourth portion of the gate electrode extend lower than the bottom surface of the gate spacer;
- a contact etch stop layer comprising a portion over and contacting the plurality of carbon nanotubes;
- and
- an inter-layer dielectric over the contact etch stop layer.
7 more elements
Dependencies are inferred from the claim text.