US 12,672,344 B2Granted

Integrated circuit structure and method of forming the same

AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.

InventorsKam-Tou Sio, Chih-Liang Chen, Charles Chew-Yuen Young, Hui-Zhong Zhuang, Jiann-Tyng Tzeng, Yi-Hsun Chiu

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Abstract

A method of forming an integrated circuit structure includes generating a first well layout pattern corresponding to fabricating a first well in the integrated circuit structure. The generating the first well layout pattern includes generating a first layout pattern having a first width, and corresponding to fabricating a first portion of the first well, and generating a second layout pattern having a second width and corresponding to fabricating a second portion of the first well. The method further includes generating a first implant layout pattern having a third width and corresponding to fabricating a first set of implants in the first portion of the first well, generating a second implant layout pattern having a fourth width and corresponding to fabricating a second set of implants in the second portion of the first well, and manufacturing the integrated circuit structure based on the above layout patterns.

Claims20

Dependent claims

A method of forming an integrated circuit structure, the method comprising:

generating a first well layout pattern corresponding to fabricating a first well in the integrated circuit structure, the first well having a first dopant type, the generating the first well layout pattern comprises:
generating a first layout pattern extending in a first direction and having a first width, the first layout pattern corresponding to fabricating a first portion of the first well;
and
generating a second layout pattern extending in the first direction, being adjacent to the first layout pattern, and having a second width greater than the first width, the second layout pattern corresponding to fabricating a second portion of the first well;
and
generating a first implant layout pattern extending in the first direction, overlapping the first layout pattern and having a third width greater than the first width, the first implant layout pattern corresponding to fabricating a first set of implants in the first portion of the first well of the integrated circuit structure, each implant of the first set of implants having the first dopant type and being separated from each other in the first direction, and at least one implant of the first set of implants being configured to be coupled to a first supply voltage;
generating a second implant layout pattern extending in the first direction, being adjacent to the first implant layout pattern, being over the second layout pattern and having a fourth width, the second implant layout pattern corresponding to fabricating a second set of implants in the second portion of the first well of the integrated circuit structure, each implant of the second set of implants having a second dopant type and being separated from each other in the first direction;
wherein at least one of the above layout patterns is stored on a non-transitory computer-readable medium, and at least one of the above operations is performed by a hardware processor;
and
manufacturing the integrated circuit structure based on at least one of the above layout patterns of the integrated circuit structure.

7 more elements

A method of forming an integrated circuit structure, the method comprising:

generating a first well layout pattern corresponding to fabricating a first well in the integrated circuit structure, the first well having a first dopant type, the generating the first well layout pattern comprises:
generating a first layout pattern extending in a first direction and having a first width, the first layout pattern corresponding to fabricating a first portion of the first well, and
generating a second layout pattern extending in the first direction, being adjacent to the first layout pattern, and having a second width greater than the first width, the second layout pattern corresponding to fabricating a second portion of the first well;
and
generating a first implant layout pattern extending in the first direction, overlapping the first layout pattern and having a third width greater than the first width, the first implant layout pattern corresponding to fabricating a first set of implants in the first portion of the first well of the integrated circuit structure, each implant of the first set of implants having the first dopant type and being separated from each other in the first direction, and at least one implant of the first set of implants being configured to be coupled to a first supply voltage;
and
generating a set of standard cell layout patterns adjacent to the first well layout pattern and the first implant layout pattern, the set of standard cell layout patterns corresponding to fabricating a set of standard cells of the integrated circuit structure, the set of standard cells comprising a set of transistors, and the set of standard cells being arranged in rows and columns,
wherein at least one of the above layout patterns is stored on a non-transitory computer-readable medium, and at least one of the above operations is performed by a hardware processor;
and
manufacturing the integrated circuit structure based on at least one of the above layout patterns of the integrated circuit structure.

7 more elements

A method of forming an integrated circuit structure, the method comprising:

generating a first well layout pattern corresponding to fabricating a first well in the integrated circuit structure, the first well having a first dopant type, the generating the first well layout pattern comprises:
generating a first layout pattern extending in a first direction and having a first width, the first layout pattern corresponding to fabricating a first portion of the first well;
and
generating a second layout pattern extending in the first direction, being adjacent to the first layout pattern, and having a second width greater than the first width, the second layout pattern corresponding to fabricating a second portion of the first well;
and
placing a first implant layout pattern over the first layout pattern, the first implant layout pattern extending in the first direction, and having a third width greater than the first width, the first implant layout pattern corresponding to fabricating a first set of implants in the first portion of the first well of the integrated circuit structure, each implant of the first set of implants having the first dopant type and being separated from each other in the first direction, and at least one implant of the first set of implants being configured to be coupled to a first supply voltage;
placing a second implant layout pattern over the second layout pattern, the second implant layout pattern extending in the first direction, being adjacent to the first implant layout pattern, and having a fourth width, the second implant layout pattern corresponding to fabricating a second set of implants in the second portion of the first well of the integrated circuit structure, each implant of the second set of implants having a second dopant type and being separated from each other in the first direction;
wherein at least one of the above layout patterns is stored on a non-transitory computer-readable medium, and at least one of the above operations is performed by a hardware processor;
and
manufacturing the integrated circuit structure based on at least one of the above layout patterns of the integrated circuit structure.

7 more elements

Dependencies are inferred from the claim text.

Facts

Application: 18/317,440Filed 15 May 2023 · division
Priority: 29 Nov 2016
Published: US 2023/0282639 A17 Sep 2023
Granted: 30 Jun 2026
Term ends: Not estimatedThe source records don’t support an estimate.

Classification11 codes

H10D 84/82
Characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs: of only…
H10D 84/0156
The components including insulated gates, e.g. IGFETs: manufacturing their doped wells
H10D 84/85
Of only insulated-gate FETs [IGFET]: complementary IGFETs, e.g. CMOS
H10D 84/90
Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers:…

Family

Application62/427,558Us provisional application · filed 29 Nov 2016
Application15/782,183Parent of this division · filed 12 Oct 2017
Application16/940,334Parent of this continuation · filed 27 Jul 2020
US 10,734,377 B2Parent of this division · filed 4 Aug 2020
Application17/132,447Parent of this division · filed 23 Dec 2020
US 10,879,229 B2Parent of this continuation · filed 29 Dec 2020
US 2023/0282639 A1Pre-grant publication · published 7 Sep 2023
US 11,652,102 B2Parent of this division
Application17/132,447Parent of this continuation
Application16/940,334Parent of this division
US 2018/0151559 A1Published application
US 2020/0357793 A1Published application
US 2021/0118868 A1Published application
US 12,672,344 B2This patent

From the US filing history. Foreign family members aren’t listed.