Silicon carbide semiconductor device

A silicon carbide semiconductor device, comprising:

• a silicon carbide semiconductor substrate having a first main surface and a second main surface on a side opposite to that of the first main surface;
• a source electrode formed on the first main surface;
• a plurality of side-by-side source contact regions that are connecting portions between the first main surface and the source electrode and that extend along the first main surface;
• a plurality of trenches formed side by side in a direction parallel to a long side of the source contact regions, in the first main surface between the source contact regions, which are adjacent to each other in a short-side direction of the source contact regions;
• a gate electrode formed in the trenches via an insulating film;
• a first semiconductor region of a first conductivity type;
• a second semiconductor region of a second conductivity type different from the first conductivity type;
• a third semiconductor region of the first conductivity type that is in contact with a first lateral surface of the trench and to which a source potential is applied;
• a fourth semiconductor region of the second conductivity type that is in contact with the first lateral surface of the trench and that has an impurity concentration lower than that of the second semiconductor region;
• a fifth semiconductor region of the first conductivity type that is in contact with the first lateral surface of the trench, the first semiconductor region, the second semiconductor region, the third semiconductor region, the fourth semiconductor region, and the fifth semiconductor region being formed in order from the second main surface toward the first main surface in the silicon carbide semiconductor substrate;
• and
• a sixth semiconductor region of the first conductivity type that is formed in the silicon carbide semiconductor substrate so as to be separated from the trench and that connects the fifth semiconductor region and the first semiconductor region,
• wherein the third semiconductor region is separated from the first semiconductor region, the fifth semiconductor region, and the sixth semiconductor region,
• wherein the gate electrode, and the third semiconductor region, the fourth semiconductor region, and the fifth semiconductor region, which are regions adjacent to the first lateral surface of the trench and overlapping each other in plan view, constitute a field effect transistor, and
• wherein a channel of the field effect transistor is generated between the third semiconductor region and the fifth semiconductor region in the fourth semiconductor region in contact with the first lateral surface of the trench.