Semiconductor devices including buffer layer structure

A semiconductor device comprising:

• a first sheet pattern and a second sheet pattern spaced apart from each other on a substrate, each of the first and second sheet patterns extending in a first direction;
• a third sheet pattern and a fourth sheet pattern spaced apart from each other on the second sheet pattern, each of the third and fourth sheet patterns extending in the first direction;
• a gate structure on the substrate, the gate structure extending in a second direction crossing the first direction and penetrating the first to fourth sheet patterns, the gate structure being between ones of the first to fourth sheet patterns;
• a first source/drain region on a first portion of a side surface of the gate structure and electrically connected to the first sheet pattern and the second sheet pattern;
• a second source/drain region on a second portion of the side surface of the gate structure and electrically connected to the third sheet pattern and the fourth sheet pattern;
• and
• a buffer layer between at least a portion of the substrate and the first sheet pattern, the buffer layer comprising germanium,
• wherein a thickness of the buffer layer is greater than a thickness of each of the first to fourth sheet patterns,
• wherein the substrate includes a fin pattern between the first sheet pattern and the buffer layer,
• wherein the substrate and the fin pattern are integrated to each other,
• wherein the fin pattern is a monolithic structure,
• wherein the buffer layer is different from the substrate,
• wherein the first source/drain region is between the fin pattern and the second source/drain region, and
• wherein the buffer layer is not in contact with each of the first sheet pattern, the second sheet pattern, the third sheet pattern, and the fourth sheet pattern.

A semiconductor device comprising:

• a bit line on a substrate, the bit line extending in a first direction perpendicular to a top surface of the substrate;
• a plurality of semiconductor patterns electrically connected to the bit line and extending in a second direction parallel to the top surface of the substrate;
• a plurality of gate patterns extending in a third direction different from the first and second directions, the plurality of gate patterns alternating with the plurality of semiconductor patterns in a stacked structure;
• an information storage element electrically connected to the plurality of semiconductor patterns;
• and
• a buffer layer between at least a portion of the substrate and the plurality of semiconductor patterns and comprising germanium,
• wherein the substrate includes a fin pattern between the buffer layer and the plurality of semiconductor patterns in the first direction,
• wherein the substrate and the fin pattern are integrated to each other,
• wherein the fin pattern is a monolithic structure,
• wherein the buffer layer is different from the substrate, and
• wherein the buffer layer is not in contact with the plurality of semiconductor patterns.