US 12,671,612 B1 · Multi-tap decision feedback equalizer (DFE) training in a memory physical (PHY) layer

Abstract

Technologies for optimizing multi-tap Decision Feedback Equalizer (DFE) training in the memory physical (PHY) layer may be described. A receiver circuit includes analog and digital circuitry. The analog circuitry includes a single de-serializer and a set of DFE taps. The digital circuitry includes a register to store a copy of a set of training patterns. The digital circuitry performs byte alignment using a first training pattern. The digital circuitry may match error bits received from the single de-serializer with data bits of the copy of the set of training patterns. The digital circuitry may calibrate the set of DFE taps using the error bits and the data bits.

Claims17

Dependent claims

A receiver circuit of a physical layer (PHY) of a memory controller, the receiver circuit comprising;

a data path configured to receive a signal from a dynamic random access memory (DRAM) device at a data pin over a channel, the data path comprising a plurality of Decision Feedback Equalizer (DFE) taps and only one de-serializer block configured to produce received data;
and
a digital logic coupled to the data path, wherein the digital logic is configured to perform byte alignment by comparing the received data with first data stored in a register of the digital logic, wherein the plurality of DFE taps is calibrated by comparing the received data with second data stored in the register, wherein the digital logic comprises a counter configured to select portions of the second data for comparisons with the received data.

A receiver circuit comprising:

analog circuitry comprising a single de-serializer and a plurality of Decision Feedback Equalizer (DFE) taps, wherein, during a training mode of the receiver circuit, the analog circuitry is configured to receive a first training pattern in a first stage of the training mode and a plurality of training patterns in a second stage of the training mode;
and
digital circuitry coupled to the analog circuitry, the digital circuitry comprising a register configured to store a copy of the plurality of training patterns, wherein the digital circuitry is configured to perform byte alignment using the first training pattern in the first stage, wherein, in the second stage, the digital circuitry is configured to match error bits received from the single de-serializer with data bits of the copy of the plurality of training patterns, and wherein, in the second stage, the digital circuitry is configured to calibrate the plurality of DFE taps using the error bits and the data bits.

A system comprising:

a dynamic random access memory (DRAM) device comprising a first-in-first-out (FIFO) configured to store a plurality of training patterns, the DRAM device is configured to send first data bits of the plurality of training patterns;
and
a memory controller coupled to the DRAM device via a channel, wherein the memory controller comprises a register configured to store a copy of the plurality of training patterns, wherein the memory controller comprises:
analog circuitry comprising a single de-serializer and a plurality of Decision Feedback Equalizer (DFE) taps, the single de-serializer is configured to only provide error bits corresponding to the first data bits received from the DRAM device;
and
digital circuitry coupled to the analog circuitry, wherein the digital circuitry is configured to perform byte alignment using a toggling pattern, and wherein the digital circuitry is configured to calibrate the plurality of DFE taps using the error bits received from the single de-serializer and matching second data bits of the copy of the plurality of training patterns stored in the register.

3 more elements

Dependencies are inferred from the claim text.

Multi-tap decision feedback equalizer (DFE) training in a memory physical (PHY) layer

Life of this patent

Multi-tap decision feedback equalizer (DFE) training in a memory physical (PHY) layer

Life of this patent

Abstract

Claims17