Dual-phase and impulse based ultra-wideband architecture
AssigneeInfineon Technologies AG
InventorsAjinder Pal Singh, Cecilia Carbonelli, Daniel Lee
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Abstract
An ultra-wideband receiver with enhanced signal detection capabilities is provided. In one example, the receiver includes a first processing path comprising first de-spreading circuitry that de-spreads a received UWB signal based on a first bit value to generate a first magnitude value, a second processing path comprising second de-spreading circuitry that de-spreads the received UWB signal based on a second bit value to generate a second magnitude value, and data recovery circuitry. Data recovery circuitry is configured to compare the first magnitude value to the second magnitude value and output a bit value based on the comparison.
Claims20
An ultra-wideband (UWB) receiver, comprising:
- a first processing path comprising first de-spreading circuitry that de-spreads a received UWB signal based on a first bit value to generate a first magnitude value;
- a second processing path comprising second de-spreading circuitry that de-spreads the received UWB signal based on a second bit value to generate a second magnitude value;
- and
- data recovery circuitry configured to
- compare the first magnitude value to the second magnitude value;
- and
- output a bit value based on the comparison.
A method, comprising:
- de-spreading a received UWB signal based on a first bit value to generate a first magnitude value;
- de-spreading the received UWB signal based on a second bit value to generate a second magnitude value;
- comparing the first magnitude value to the second magnitude value;
- and
- outputting a bit value based on the comparison.
An ultra-wideband (UWB) receiver, comprising:
- de-spreading circuitry that de-spreads a received UWB signal based on a template to generate a de-spread received UWB signal;
- I/Q splitter circuitry configured to split de-spread received UWB signal into a I component and a Q component;
- I component integrator/analog-to-digital converter (ADC) circuitry configured to sum the I component over a symbol period and output a digital I component;
- Q component integrator/ADC circuitry configured to sum the Q component over a symbol period and output a digital Q component;
- and
- a polar converter configured to convert the digital I component and the digital Q component to a magnitude value and a phase value.
Dependencies are inferred from the claim text.