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US 12,671,443 B2Granted
Error correction
AssigneeMicron Technology, Inc.
InventorsMarco Sforzin, Paolo Amato, Yang Lu
Life of this patent
Estimating the term…
Abstract
Methods, systems, and devices related to mapping a plurality of pairs of bits of a memory transfer block (MTB) to a plurality of linked (LK) die input/output (LDIO) lines coupling a LK die to an interface (IF) die. The plurality of pairs of bits of the MTB can be communicated from the LK die to the IF die via the plurality of LDIO lines. Responsive to a failure of one of the plurality of LDIO lines, a Bose-Chaudhuri-Hocquenghem (BCH) error correction can be performed on the pairs of bits mapped to the failed LDIO line. Each of the plurality of pairs of bits is a respective symbol for the BCH error correction.
Claims20
A method, comprising:
- partitioning a plurality of bits of a memory transfer block (MTB) into a plurality of pairs of bits;
- generating symbols based on the partitioned pairs of bits and corresponding to each of the pair of bits;
- communicating the plurality of pairs of bits of the MTB from a linked (LK) die to an interface (IF) die via a plurality of linked die input/output (LDIO) lines, wherein two pairs of bits of the plurality of pairs of bits are distributed to each LDIO line of the plurality of LDIO lines;
- mapping the plurality of pairs of bits to pins of a data bus coupled to the IF die, wherein both of the two pairs of bits for each of the plurality of LDIO lines are mapped to the same pin of the data bus;
- and
- responsive to detecting a failure on the data bus corresponding to one of the plurality of LDIO lines, performing a Bose-Chaudhuri-Hocquenghem (BCH) error correction on the two pairs of bits mapped to the failed LDIO line, wherein each symbol corresponding to the plurality of pairs of bits is a respective symbol for the BCH error correction.
3 more elements
An apparatus, comprising:
- a first linked (LK) die;
- a first interface (IF) die coupled to the first LK die by a first plurality of LK die input/output (LDIO) lines;
- control circuitry coupled to the first IF die and configured to direct:
- association of a first plurality of subsets of bits of a memory transfer block (MTB) to respective ones of the first plurality of LDIO lines;
- communication of the first plurality of subsets of bits from the first LK die to the first IF die via the first plurality of LDIO lines;
- and
- responsive to an error in communication of the first plurality of subsets of bits, performance of a Bose-Chaudhuri-Hocquenghem (BCH) error correction on the first plurality of subsets of bits;
- a second LK die;
- and
- a second IF die coupled to the second LK die by a second plurality of LDIO lines, wherein the control circuitry is coupled to the second IF die and is further configured to direct:
- association of a second plurality of subsets of bits of the MTB to respective ones of the second plurality of LDIO lines;
- communication of the second plurality of subsets of bits from the second LK die to the second IF die via the second plurality of LDIO lines;
- and
- responsive to an error in communication of the second plurality of subsets of bits, performance of the BCH error correction on the second plurality of subsets of bits.
11 more elements
An apparatus, comprising:
- control circuitry configured to:
- partition a first plurality of bits of a memory transfer block (MTB) into a first plurality of subsets of bits;
- partition a second plurality of bits of the MTB into a second plurality of subsets of bits;
- generate symbols corresponding to respective pairs of bits of the MTB, wherein the first plurality of subsets of bits and the second plurality of subsets of bits each include two symbols;
- communicate the plurality of pairs of bits of the MTB from a linked (LK) die to an interface (IF) die via a plurality of linked die input/output (LDIO) lines, wherein two pairs of bits of the plurality of pairs of bits are distributed to each LDIO line of the plurality of LDIO lines;
- map the plurality of pairs of bits to pins of a data bus coupled to the IF die, wherein both of the two pairs of bits for each of the plurality of LDIO lines are mapped to the same pin of the data bus;
- and
- responsive to a failed communication of the MTB, performing a Bose-Chaudhuri-Hocquenghem (BCH) error correction on the MTB, wherein each of the first plurality of subsets of bits and the second plurality of subsets of bits include two pairs of bits, wherein each pair of bits is a respective symbol for the BCH error correction.
5 more elements
Dependencies are inferred from the claim text.