Systems and methods for block-kronecker based low density parity check (LDPC) code with 5/6 code rate
AssigneeAvago Technologies International Sales Pte. Limited
InventorsRethnakaran Pulikkoonattu, Andrew Blanksby, Vinko Erceg
Life of this patent
Estimating the term…
Abstract
An apparatus may include a transmitter and one or more processors. The one or more processors may identify, based on a first parity check matrix of a first quasi-cyclic-low-density parity-check (QC-LDPC) code according to a code rate of 5/6, a second parity check matrix corresponding to a first exponent matrix comprising 384 values for a second QC-LDPC code. The second QC-LDPC code may have a code block size that is twice a code block size of the first QC-LDPC code. The one or more processors may encode data using the second parity check matrix. The transmitter may be configured to transmit the encoded data.
Claims18
A method, comprising:
- identifying, by baseband circuitry of a first device, a first parity check matrix of a first quasi-cyclic-low-density parity-check (QC-LDPC) code having a code rate of 5/6;
- determining, by the baseband circuitry, based at least on a result of a Khatri-Rao product of the first parity check matrix and a first binary matrix having the same dimensions as dimensions of an exponent matrix of the first parity check matrix, a second parity check matrix corresponding to a first exponent matrix comprising 384 values for a second QC-LDPC having a code block size that is twice a code block size of the first QC-LDPC code;
- encoding, by an encoder of the baseband circuitry of the first device while concurrently encoding other data, data using the second parity check matrix to increase a gain in signal-to-noise ratio (SNR) across multiple modulation schemes over wireless channels;
- and
- transmitting, by a transmitter of the first device, the encoded data.
An apparatus comprising:
- a transmitter and baseband circuitry including an encoder, wherein
- the baseband circuitry is configured to:
- identify a first parity check matrix of a first quasi-cyclic-low-density parity-check (QC-LDPC) code having a code rate of 5/6;
- and
- determine, based at least on a result of a Khatri-Rao product of the first parity check matrix and a first binary matrix having the same dimensions as dimensions of an exponent matrix of the first parity check matrix, a second parity check matrix corresponding to a first exponent matrix comprising 384 values for a second QC-LDPC having a code block size that is twice a code block size of the first QC-LDPC code,
- the encoder is configured to encode, while concurrently encoding other data, data using the second parity check matrix to increase a gain in signal-to-noise ratio (SNR) across multiple modulation schemes over wireless channels, and
- the transmitter is configured to transmit the encoded data.
An apparatus comprising:
- a receiver configured to receive encoded data to increase a gain in signal-to-noise ratio (SNR) across multiple modulation schemes over wireless channels, wherein the encoded data is encoded using a second quasi-cyclic-low-density parity-check (QC-LDPC) code according to a code rate of 5/6, wherein the second QC-LDPC code has a code block size that is twice a code block size of a first QC-LDPC code;
- and
- baseband circuitry configured to:
- identify a first parity check matrix of the first QC-LDPC code having a code rate of 5/6;
- determine, based at least on a result of a Khatri-Rao product of the first parity check matrix and a first binary matrix having the same dimensions as dimensions of an exponent matrix of the first parity check matrix, a second parity check matrix corresponding to a first exponent matrix comprising 384 values for the second QC-LDPC;
- and
- decode, while concurrently decoding other data, the received encoded data using the second parity check matrix.
Dependencies are inferred from the claim text.