Autonomous synchronization architecture for massively time-interleaved analog to digital converters

An apparatus comprising:

• a first phase interpolator (PI) of a plurality of phase interpolators, the first phase interpolator configured to receive a first clock signal and generate a second clock signal based on the first clock signal;
• a first analog to digital converter-group (ADC-group) of a plurality of ADC-groups, wherein the first ADC-group comprises:
• a clock divider configured to generate a third clock signals based, at least in part, on the second clock signal;
• a token generator configured to generate a first token signal based, at least in part, on the second clock signal;
• a first sub-analog to digital converter (sub-ADC) of one or more sub-ADCs comprising:
• one or more unit-analog to digital converters (unit-ADCs) configured to sample an input signal based, at least in part, on the third clock signal;
• a first phase detector configured to generate a first output indicating a phase of the first clock signal relative to a phase of the third clock signal, and a second output indicating a phase of a first reference signal relative to the phase of the third clock signal;
• and
• a second phase detector configured to generate a third output indicating a phase of the token signal relative to a second reference signal;
• and
• control logic configured to:
• perform a foreground calibration, wherein the foreground calibration is configured to cause the first token signal of the first ADC-group to be aligned with a second token signal of a second ADC-group;
• and
• perform a background calibration, wherein the background calibration is configured to cause the third clock signal to be aligned with the first clock signal such that a first time margin is created between a falling edge of the first clock signal and a falling edge of the third clock signal.

A system for analog to digital converter calibration comprising:

• a multi-group multiple input multiple output phase interpolator (MG-MIMO-PI) comprising one or more multiple input multiple output phase interpolators (MIMO-PI), the MG-MIMO-PI configured to receive a first clock signal, wherein a first MIMO-PI of the one or more MIMO-PIs is configured to generate a second clock signal based on the first clock signal;
• a first analog to digital converter (ADC) comprising:
• a clock divider configured to generate a third clock signals based, at least in part, on the second clock signal;
• a token generator configured to generate a first token signal based, at least in part, on the second clock signal;
• control logic configured to:
• perform a foreground calibration, wherein the foreground calibration is configured to cause the first token signal to be aligned with a second token signal of a second ADC;
• and
• perform a background calibration, wherein the background calibration is configured to cause the third clock signal to be aligned with the first clock signal such that a first time margin is created between a falling edge of the first clock signal and a falling edge of the third clock signal.