Error detectors and memory devices having error detectors therein, and methods of performing error detection

A memory device, comprising:

• a first error detector configured to generate a first interval signal and a second interval signal having a duty cycle of a first period based on a first quadrature clock signal, and detect a first error in a first inverted in-phase signal of the first quadrature clock signal based on the first interval signal and the second interval signal;
• a second error detector configured to generate a third interval signal and a fourth interval signal having a duty cycle of a second period based on the first quadrature clock signal, and detect a second error in a first quadrature signal of the first quadrature clock signal based on the third interval signal and the fourth interval signal;
• a third error detector configured to generate a fifth interval signal and a sixth interval signal having a duty cycle of a third period based on the first quadrature clock signal, and detect a third error in a first inverted quadrature signal of the first quadrature clock signal based on the fifth interval signal and the sixth interval signal;
• a delay cell configured to generate a second inverted in-phase signal by delaying the first inverted in-phase signal based on the first error, generate a second quadrature signal by delaying the first quadrature signal based on the second error, and generate a second inverted quadrature signal by delaying the first inverted quadrature signal based on the third error;
• and
• a memory chip configured to perform a memory operation based on the second inverted in-phase signal, the second quadrature signal, the second inverted quadrature signal, and the first quadrature clock signal.

An error detecting method for a memory device, comprising:

• receiving a plurality of phase signals;
• generating a plurality of interval signals including a first interval signal and a second interval signal having equivalent duty cycles based on the plurality of phase signals;
• and
• determining an error in any one of the plurality of phase signals based on the first interval signal and the second interval signal among the plurality of interval signals,
• wherein said generating of the first interval signal includes generating the first interval signal having a rising edge corresponding to a rising edge of a first phase signal and a falling edge corresponding to a rising edge of a second phase signal.