Systems, methods, and apparatus to support multiple synchronous clocks with a single clock mesh
AssigneeMarvell Asia Pte Ltd
InventorsHarry Linzer, Kevin William Gorman, Zahi S. Abuhamdeh
Life of this patent
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Abstract
A single clock mesh is configured to provide a first clock signal at a first frequency. A number of divided clock signals are generated, each divided clock signal being at a frequency that is a respective integer division of the first frequency. The divided clock signals are received from a divider and output by a clock controller along with corresponding enable signals. For each divided clock, a shaped clock signal is generated. The shaped clock signal has rising edges and falling edges that algin with rising edges and falling edges of the first clock signal provided by the single clock mesh.
Claims20
An electronic device for supporting multiple synchronous clocks with a single clock mesh, the electronic device comprising:
- a single clock mesh configured to provide a first clock signal at a first frequency;
- divider circuitry configured to generate a plurality of divided clock signals, each divided clock signal being at a frequency that is a respective integer division of the first frequency;
- an on-chip clock controller configured to receive the divided clock signals, and output the divided clock signals and corresponding enable signals for each divided clock signal;
- and
- clock shaper circuitry configured to generate, for each divided clock signal, a shaped clock signal having rising edges and falling edges aligned with rising edges and falling edges of the first clock signal provided by the single clock mesh.
A method for supporting multiple synchronous clocks with a single clock mesh, the method comprising:
- providing a first clock signal at a first frequency using a single clock mesh;
- generating a plurality of divided clock signals, each divided clock signal being at a frequency that is a respective integer division of the first frequency;
- receiving the divided clock signals and outputting the divided clock signals and corresponding enable signals for each divided clock signal;
- and
- generating, for each divided clock signal, a shaped clock signal having rising edges and falling edges aligned with rising edges and falling edges of the first clock signal provided by the single clock mesh.
A system for supporting multiple synchronous clocks with a single clock mesh, comprising:
- a clock mesh configured to provide a first clock signal at a first frequency;
- one or more electronic components, each of which is configured to operate using a respective clock signal at a respective different frequency lower than the first frequency, the respective different frequency being an integer division of the first frequency, a plurality of different frequencies being used among the one or more electronic components;
- and
- clock circuitry configured to:
- generate, from the first clock signal, one or more divided clock signals, wherein each divided clock signal has a frequency that is an integer division of the first frequency, and wherein each respective divided clock signal corresponds to a respective frequency among the plurality of different frequencies, and
- shape each of the one or more divided clock signals such that each divided clock signal has a rising edge that aligns with a rising edge of the first clock signal and a falling edge that aligns with a falling edge of the first clock signal.
Dependencies are inferred from the claim text.