US 12,671,418 B2Granted

Signal generation circuit and control device

AssigneeVanguard International Semiconductor Corporation

InventorsJung-Tsun Chuang, Chieh-Yao Chuang, Wei-Ting Chen

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Abstract

A signal generator circuit is provided. The gate of a first transistor and the drain of a second transistor are coupled to a first output terminal. The sources of the first and second transistors are coupled to a first power terminal. The drains of the first and third transistors, and the gate of the second transistor are coupled to a second output terminal. The gate of the third transistor is coupled to a second power terminal. The source of the third transistor is coupled to a third power terminal. A fourth transistor is coupled to the second power terminal and the first output terminal. When the third transistor is turned off, a first bias circuit turns on the fourth transistor. A second bias circuit provides a first predetermined voltage to the second transistor. A third bias circuit provides a second predetermined voltage to the first transistor.

Claims18

Dependent claims

A signal generation circuit comprising:

a first transistor comprising a first gate, a first source and a first drain, wherein the first gate is coupled to a first output terminal, the first source is coupled to a first power terminal, and the first drain is coupled to a second output terminal;
a second transistor comprising a second gate, a second source and a second drain, wherein the second gate is coupled to the second output terminal, the second source is coupled to the first power terminal, and the second drain is coupled to the first output terminal;
a third transistor comprising a third gate, a third source and a third drain, wherein the third gate is coupled to a second power terminal, the third source is coupled to a third power terminal, and the third drain is coupled to the second output terminal;
a fourth transistor comprising a fourth gate, a fourth source and a fourth drain, wherein the fourth source is coupled to the second power terminal, and the fourth drain is coupled to the first output terminal;
a first bias circuit coupled to the fourth gate to turn on the fourth transistor in response to the third transistor not being turned on;
a second bias circuit coupled to the second output terminal to provide a first predetermined voltage to the second gate;
and
a third bias circuit coupled to the first output terminal to provide a second predetermined voltage to the first gate,
wherein:
the first and second transistors are P-type MOS transistors, and the third and fourth transistors are N-type MOS transistors, in a power-on period:
a voltage of the first power terminal and a voltage of the second power terminal are increased,
in response to the voltage of the first power terminal being equal to a first target value and the voltage of the second power terminal being equal to a second target value, the first and fourth transistors are turned off and the second and third transistors are turned on,
the first target value is higher than the second target value, and the second target value is higher than a voltage of the third power terminal.

10 more elements

A control device comprising:

a signal generation circuit comprising:
a first transistor comprising a first gate, a first source and a first drain, wherein the first gate is coupled to a first output terminal, the first source is coupled to a first power terminal, and the first drain is coupled to a second output terminal;
a second transistor comprising a second gate, a second source and a second drain, wherein the second gate is coupled to the second output terminal, the second source is coupled to the first power terminal, and the second drain is coupled to the first output terminal;
a third transistor comprising a third gate, a third source and a third drain, wherein the third gate is coupled to a second power terminal, the third source is coupled to a third power terminal, and the third drain is coupled to the second output terminal;
a fourth transistor comprising a fourth gate, a fourth source and a fourth drain, wherein the fourth source is coupled to the second power terminal, and the fourth drain is coupled to the first output terminal;
a first bias circuit coupled to the fourth gate to turn on the fourth transistor in response to the third transistor not being turned on;
a second bias circuit coupled to the second output terminal to provide a first predetermined voltage to the second gate;
and
a third bias circuit coupled to the first output terminal to provide a second predetermined voltage to the first gate;
an inverter inverting a voltage of the first output terminal to generate an inverted signal;
a fifth transistor coupled between the first power terminal and a third output terminal or between the second power terminal and the third output terminal;
a sixth transistor coupled between the third output terminal and the third power terminal;
and
a logic circuit providing a control signal to a gate of the fifth transistor and a gate of the sixth transistor,
wherein:
in a power-on period:
a voltage of the first power terminal and a voltage of the second power terminal are increased,
in response to the voltage of the first power terminal reaching a target value, the logic circuit generates the control signal according to input data,
in a power-off period:
the voltages of the first and second power terminals are reduced,
in response to the voltage of the first power terminal being equal to a voltage of the third power terminal, the logic circuit generates the control signal according to the inverted signal.

18 more elements

Dependencies are inferred from the claim text.

Facts

Application: 18/904,842Filed 2 Oct 2024
Published: US 2026/0095181 A12 Apr 2026
Granted: 30 Jun 2026
Term ends: Not estimatedThe source records don’t support an estimate.

Classification4 codes

H03K 19/00384
Modifications for compensating variations of temperature, supply voltage or other physical parameters: in field effect transistor circuits
H03K 19/0005
Logic circuits, i.e. having at least two inputs acting on one output ; Inverting circuits: modifications of input or output impedance
H03K 19/00361
Modifications for eliminating interference or parasitic voltages or currents: in field effect transistor circuits
H03K
Pulse technique