Interlock device, energy storage system, control method, and device thereof

An interlock device, comprising:

• a first interlock circuit (A1), a first drive processing circuit (A2), a first drive status feedback circuit (A3), a second interlock circuit (B1), a second drive processing circuit (B2), and a second drive status feedback circuit (B3);
• the first interlock circuit (A1) is provided with a first input terminal (A11) and a second input terminal (A12), the first interlock circuit (A1) is configured to output a first low level signal when the first input terminal (A11) of the first interlock circuit (A1) and the second input terminal (A12) of the first interlock circuit (A1) input high level signals, and the first interlock circuit (A1) is configured to output a first high level signal otherwise;
• the first drive processing circuit (A2) is configured to receive the first high level signal or the first low level signal output by the first interlock circuit (A1), the first drive processing circuit (A2) is configured to output a second high level signal when receiving the first low level signal, and the first drive processing circuit (A2) is configured to output a second low level signal when receiving the first high level signal;
• the first drive status feedback circuit (A3) is configured to receive the second high level signal or the second low level signal output by the first drive processing circuit (A2), the first drive status feedback circuit (A3) is configured to output a third high level signal through an output terminal of the first drive status feedback circuit (A3) when receiving the second low level signal, and the first drive status feedback circuit (A3) is configured to output a third low level signal through the output terminal of the first drive status feedback circuit (A3) when receiving the second high level signal;
• the second interlock circuit (B1) is provided with a first input terminal (B11) and a second input terminal (B12), the second interlock circuit (B1) is configured to output a fourth low level signal when the first input terminal (B11) of the second interlock circuit (B1) and the second input terminal (B12) of the second interlock circuit (B1) input high level signals, and the second interlock circuit (B1) is configured to output a fourth high level signal otherwise;
• the second drive processing circuit (B2) is configured to receive the fourth high level signal or the fourth low level signal output by the second interlock circuit (B1), the second drive processing circuit (B2) is configured to output a fifth high level signal when receiving the fourth low level signal, and the second drive processing circuit (B2) is configured to output a fifth low level signal when receiving the fourth high level signal;
• the second drive status feedback circuit (B3) is configured to receive the fifth high level signal or the fifth low level signal output by the second drive processing circuit (B2), the second drive status feedback circuit (B3) is configured to output a sixth high level signal through an output terminal of the second drive status feedback circuit (B3) when receiving the fifth low level signal;
• and the second drive status feedback circuit (B3) is configured to output a sixth low level signal through the output terminal of the second drive status feedback circuit (B3) when receiving the fifth high level signal;
• and
• the second input terminal (A12) of the first interlock circuit (A1) is configured to receive the sixth high level signal or the sixth low level signal output by the second drive status feedback circuit (B3), and the second input terminal (B12) of the second interlock circuit (B1) is configured to receive the third high level signal or the third low level signal output by the first drive status feedback circuit (A3).