Analog signal processing circuit and method for eliminating DC offset voltage

An analog signal processing circuit, comprising:

• a) a front-stage processing module configured to receive an analog signal to generate a first differential signal;
• b) at least one switched capacitor circuit coupled to the front-stage processing module for receiving the first differential signal, and being configured to integrate or sample and hold the first differential signal to generate a second differential signal;
• and
• c) wherein the front-stage processing module and the at least one switched capacitor circuit receive synchronous control signals, and the at least one switched capacitor circuit operates in different operating modes at a first phase and a second phase of an operation cycle of the synchronous control signals, in order to eliminate DC offset voltages in the front-stage processing module and the at least one switched capacitor circuit;
• d) wherein the synchronous control signals are configured as clock signals to set the first phase and the second phase;
• e) wherein the DC offset voltage in the front-stage processing module is modulated into a high-frequency square wave signal according to the synchronous control signals and
• f) wherein in one of the first phase and the second phase, capacitors in the switched capacitor circuit store the DC offset voltage in the front-stage processing module, in the other of the first phase and the second phase, and the DC offset voltage in the front-stage processing is eliminated by using the voltage stored in the one of the first phase and the second phase on the capacitors.