Multi-level conversion circuit and cycle-by-cycle protection method therefor

A cycle-by-cycle protection method for a multi-level conversion circuit, wherein the number of levels of the multi-level conversion circuit equals N which is an integer greater than or equal to 3, the multi-level conversion circuit comprises a first input terminal, a second input terminal, a first output terminal, a second output terminal, an inductor, N−1 lower switches, N−1 upper switches and N−2 flying capacitors, the first input terminal and the second input terminal are configured to receive an input voltage, the first output terminal and the second output terminal are configured to provide an output voltage, the first input terminal is electrically connected to the second output terminal when a potential at the first input terminal is lower than a potential at the second input terminal, and the first input terminal is electrically connected to the first output terminal when the potential at the first input terminal is higher than the potential at the second input terminal;

• a first terminal of the inductor is electrically connected to the second input terminal, the N−1 lower switches are electrically connected in series between a second terminal of the inductor and the second output terminal, the first lower switch and the N−1th lower switch are electrically coupled to the second terminal of the inductor and the second output terminal respectively, the N−1 upper switches are electrically connected in series between the second terminal of the inductor and the first output terminal, the first upper switch and the N−1th upper switch are electrically coupled to the second terminal of the inductor and the first output terminal respectively, the kth flying capacitor is connected between a common connection node of the kth lower switch and the k+1th lower switch and a common connection node of the kth upper switch and the k+1th upper switch, k is a positive integer less than or equal to N−2, and the cycle-by-cycle protection method comprises steps of:
• (a) when the potential at the first input terminal is lower than the potential at the second input terminal, operating the N−1 lower switches and the N−1 upper switches as N−1 main switches and N−1 synchronous rectification switches respectively, and when the potential at the first input terminal is higher than the potential at the second input terminal, operating the N−1 lower switches and the N−1 upper switches as N−1 synchronous rectification switches and N−1 main switches respectively;
• (b) controlling the N−1 main switches to operate in a normal mode, wherein in the normal mode, control signals of the ith lower switch and the ith upper switch are complementary, and i is a positive integer less than or equal to N−1;
• (c) detecting a current flowing through the inductor, and determining whether the current exceeds a threshold;
• (d) if a duty ratio of the N−1 main switches is greater than 1/(N−1), when the current exceeds the threshold, defining the main switch in an on state and having longest turn-on duration among the N−1 main switches as a target main switch, switching the target main switch to a current limiting mode for turning off the target main switch, and controlling the other main switches to maintain in the normal mode;
• and
• (e) after the target main switch is switched to the current limiting mode, if the current is lower than the threshold, at a moment when a rising edge of a control signal in a reference mode for the target main switch firstly appears, switching the target main switch to a state in the reference mode corresponding to the moment, wherein the reference mode is a mode where the N−1 main switches do not enter the current limiting mode and continuously operate in the normal mode.