Apparatuses and methods for testing memory devices
AssigneeMicron Technology, Inc.
InventorsTakamasa Suzuki, Yasushi Matsubara, Harutaka Makabe
Life of this patent
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Abstract
Self-test circuits of memory devices disclosed herein may include circuitry that adjusts the correspondence between logical and physical addresses to match pre-repair mapping of memory locations. That is, if a memory device has been repaired by remapping logical addresses to new physical addresses, the circuitry of the test circuit restores the pre-repair mapping of the memory device in some examples. In some examples, an unused global column redundancy data path may be repurposed to provide repair information to the self-test circuit to implement the pre-repair mapping.
Claims20
An apparatus comprising:
- a memory array including a plurality of column planes, wherein the plurality of column planes includes a global column redundancy plane;
- and
- a test circuit comprising:
- a comparator configured to compare internal read data from the memory array and expected read data, wherein the comparator is configured to provide error information based on comparing;
- and
- a pre-repair map logic circuit configured to;
- receive repair information and the error information and when the memory array has been repaired by remapping a logical address of a column plane of the plurality of column planes to a physical address of the global column redundancy plane, and
- remap the logical address of the column plane of the plurality of column planes to a physical address of the column plane to restore a pre-repair mapping of the error information in the test circuit.
An apparatus comprising:
- a memory array comprising a plurality of column planes;
- a global column redundancy circuit including a redundant column plane in the memory array;
- a repair circuit configured to remap logical addresses of the plurality of column planes from original physical addresses to new physical addresses of the plurality of column planes and the redundant column plane when at least one of the plurality of column planes is a defective column plane;
- and
- a test circuit including a pre-repair mapping circuit configured to receive data from at least a portion of the plurality of column planes and repair information from the global column redundancy circuit, wherein when the repair information indicates a repair has been performed on the defective column plane, the test circuit is configured to remap the logical addresses of the plurality of column planes to the original physical addresses of the plurality of column planes to restore a pre-repair mapping of the plurality of column planes within the test circuit.
A method comprising:
- receiving repair information for a plurality of column planes of a memory array at a test circuit;
- when the repair information indicates at least one of the plurality of column planes has been repaired using a redundant column plane of the memory array, restoring a pre-repair mapping of logical and physical addresses of the plurality of column planes by remapping the logical addresses to original ones of the plurality of column planes within the test circuit;
- and
- when the repair information indicates no repair has been made, maintaining the pre-repair mapping of the logical and the physical addresses of the plurality of column planes within the test circuit.
Dependencies are inferred from the claim text.