Resistive random access memory (RRAM) architecture and method

A structure comprising:

• multiple zones, wherein each zone includes:
• source lines connected to ground;
• bit lines;
• word lines;
• a zone-specific array of resistive random access memory (RRAM) cells arranged in columns and rows, wherein all RRAM cells in a column are connected between a source line and a bit line for the column and wherein all RRAM cells in a row are connected to a word line for the row;
• a zone-specific bit line biasing circuit connected to the bit lines, wherein the zone-specific bit line biasing circuit biases the bit lines with bit line voltages, respectively;
• a zone-specific word line biasing circuit connected to the word lines, wherein the zone-specific word line biasing circuit biases the word lines with word line voltages, respectively;
• a zone-specific power switch connected to the zone-specific bit line biasing circuit and to the zone-specific word line biasing circuit;
• and
• an analog block connected to the multiple zones, wherein the analog block is configured to output, to the zone-specific power switch in each zone, a first supply voltage selectable from a range of negative to positive supply voltages and a second supply voltage selectable from the range.

A method comprising:

• biasing bit lines of a structure with bit line voltages, respectively;
• and
• concurrently biasing word lines of the structure with word line voltages, respectively,
• wherein the structure includes:
• source lines connected to ground;
• the bit lines;
• the word lines;
• and an array of resistive random access memory (RRAM) cells arranged in columns and rows,
• wherein all RRAM cells in a column are connected between a source line and a bit line for the column and wherein all RRAM cells in a row are connected to a word line for the row,
• wherein each of the bit line voltages is operation-dependent, is bit line connection-dependent, and is at any one of multiple positive bit line voltage levels, a negative bit line voltage level, and ground, and
• wherein each of the word line voltages is operation-dependent, is word line connection-dependent, and is at any one of multiple positive word line voltage levels, a negative word line voltage level, and ground.