Memory system, operating method of the memory system, and interface circuit of the memory system

An operating method of a memory system comprising a memory device and a memory controller, the memory device comprising a plurality of non-volatile memories, each of the plurality of non-volatile memories being electrically connected to a buffer chip, and the memory controller being electrically connected to the buffer chip and configured to transmit a reference clock signal used in compensation of a data signal, the operating method comprising:

• generating at least one of a first delay clock signal or a second delay clock signal from the reference clock signal;
• storing a first delay clock code comprising information of the first delay clock signal;
• storing a second delay clock code comprising information of the second delay clock signal;
• and
• compensating for the data signal based on a first delay clock code and a second delay clock code,
• wherein the compensating for the data signal comprises performing a coarse locking operation on a data strobe signal based on the first delay clock code, performing a fine locking operation on the data strobe signal based on the second delay clock code, performing compensation on the data strobe signal based on a delay division generated based on the coarse locking operation and the fine locking operation, and performing compensation on the data signal based on the second delay clock signal.

An interface circuit of a memory system, the interface circuit comprising:

• a delay clock generation chain configured to generate at least one of a first delay clock signal or a second delay clock signal from a reference clock signal;
• a first register configured to store a first delay clock code comprising information of the first delay clock signal;
• and
• a second register configured to store a second delay clock code comprising information of the second delay clock signal,
• wherein the interface circuit is configured to perform a coarse locking operation on a data strobe signal based on a first delay clock code, perform a fine locking operation on the data strobe signal based on a second delay clock code, perform compensation on the data strobe signal based on a delay division generated based on the coarse locking operation and the fine locking operation, and perform compensation on the data signal based on the second delay clock signal.