Display panel and display module

A display panel, comprising:

• a display area and a peripheral area, the display area including a plurality of pixels arranged in an array extending in a first direction and a second direction, each pixel including a plurality of sub-pixels arranged in the first direction, wherein
• the peripheral area includes a first signal line arrangement region and a second signal line arrangement region that are arranged around the display area;
• the first signal line arrangement region includes a plurality of first signal lines extending in a same direction, and the second signal line arrangement region includes a plurality of second signal lines extending in a same direction;
• the first signal line arrangement region and the second signal line arrangement region are both in a shape of a narrow strip, and include borders that are close to and non-overlapping with each other, and the borders extend in a same direction;
• the display panel comprises:
• a plurality of first lead-out lines including a first reference lead-out line, data lines including a first reference data line, a plurality of second lead-out lines, and gate lines;
• wherein a border of the first signal line arrangement region proximate to the display area includes a plurality of first lead-out positions, and the plurality of first lead-out lines are led out from the plurality of first lead-out positions in a one-to-one correspondence, and are electrically connected to the plurality of first signal lines in a one-to-one correspondence;
• a first lead-out line is electrically connected to a data line;
• the plurality of first lead-out positions include a first reference lead-out position, and the first reference lead-out line is led out from the first reference lead-out position and electrically connected to the first reference data line;
• a width of the first signal line arrangement region corresponding to the first reference lead-out position is b0;
• a width b of the first signal line arrangement region corresponding to at least partially continuously distributed first target lead-out positions except for the first reference lead-out position satisfies:
• b0−[int(kΔ1/P1)](Wdata+Sdata)≤b≤b0−[int(kΔ1/P1)−1](Wdata+Sdata);
• wherein Δ1 is a distance between a first target lead-out position and the first reference lead-out position in the first direction, P1 is an arrangement period of a pixel in the first direction, k is a number of sub-pixels in the pixel, Wdata is a width of a first signal line, and Sdata is a distance between the adjacent first signal lines of the plurality of first signal lines;
• a border of the second signal line arrangement region proximate to the display area includes a plurality of second lead-out positions, and the plurality of second lead-out lines are led out from the plurality of second lead-out positions in one-to-one correspondence, and are electrically connected to the plurality of the second signal lines in one-to-one correspondence;
• a second lead-out line is electrically connected to a gate line;
• at least one first lead-out position and at least one second lead-out position are alternately arranged in the first direction.