Synaptic memory and memory array using Fowler-Nordheim timers
AssigneeWashington University
InventorsShantanu Chakrabartty, Darshit Mehta
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Abstract
An analog memory device includes a first node and a second node. The first node includes a first floating gate, a second floating gate, and a capacitor. The first node first floating gate is connected to the first node second floating gate via the capacitor. The second node includes a first floating gate, a second floating gate, and a capacitor. The second node first floating gate is connected to the second node second floating gate via the capacitor. The second node is connected to the first node, and an analog state of the first node and an analog state of the second node continuously and synchronously decay with respect to time.
Claims16
An analog memory device comprising:
- a first node comprising a first floating gate, a second floating gate, and a capacitor, where the first floating gate is connected to the second floating gate via the capacitor;
- and
- a second node comprising a first floating gate, a second floating gate, and a capacitor, where the first floating gate is connected to the second floating gate via the capacitor, and the second node is connected to the first node, and wherein an analog state of the first node and an analog state of the second node continuously and synchronously decay with respect to time, wherein the first node and the second node are configured such that a charge applied the first or second floating gate of the first or second nodes modifies a shape of a barrier of the associated first or second floating gate to enable Fowler-Nordheim quantum tunneling of electrons through the barrier.
An adaptive synaptic array comprising:
- a plurality of analog memory devices driven by Fowler-Nordheim quantum tunneling, wherein each analog memory device of the plurality of the analog memory devices comprises:
- a first node comprising a first floating gate, a second floating gate and a capacitor, where the first floating gate is connected to the second floating gate via the capacitor;
- and
- a second node comprising a first floating gate, a second floating gate and a capacitor, where the first floating gate is connected to the second floating gate via the capacitor, and the second node is connected to the first node, and wherein an analog state of the first node and an analog state of the second node continuously and synchronously decay with respect to time, wherein the first node and the second node of each analog memory device are configured such that a charge applied the first or second floating gate of the first or second nodes modifies a shape of a barrier of the associated first or second floating gate to enable Fowler-Nordheim quantum tunneling of electrons through the barrier.
A method of machine learning using an adaptive synaptic array comprising a plurality of analog memory devices, each analog memory device including a first node comprising a first floating gate, a second floating gate and a capacitor, where the first floating gate is connected to the second floating gate via the capacitor, and a second node comprising a first floating gate, a second floating gate and a capacitor, where the first floating gate is connected to the second floating gate via the capacitor, and the second node is connected to the first node, and wherein an analog state of the first node and an analog state of the second node continuously and synchronously decay with respect to time, and the first node and the second node of each analog memory device are configured such that a charge applied the first or second floating gate of the first or second nodes modifies a shape of a barrier of the associated first or second floating gate to enable Fowler-Nordheim quantum tunneling of electrons through the barrier the method comprising:
- selecting a network to be trained, the selected network having a plurality of learnable parameters;
- assigning each learnable parameter to a different analog memory device of the adaptive synaptic array;
- storing a weight for each learnable parameter in its assigned analog memory device through application of a charge to one or both of the first and second nodes to modify the shape of the barrier of the associated first or second floating gate of the one or both of the first and second nodes;
- and
- updating the weight of each learnable parameter in its assigned memory device in each training iteration of the selected network.
Dependencies are inferred from the claim text.