Testing circuitry and methods for analog neural memory in artificial neural network

A system comprising:

• a plurality of analog neural non-volatile memory cells in an array of analog neural non-volatile memory cells;
• and
• test control logic to perform a checkerboard verification test comprising:
• programming a first group of analog neural non-volatile memory cells in a plurality of analog neural non-volatile memory cells with a level corresponding to the smallest cell current among N levels, where N is a number of different levels that can be stored in any of the analog neural non-volatile memory cells and where the plurality of analog neural non-volatile memory cells is fewer than all of the analog neural non-volatile memory cells in the array;
• programming a second group of analog neural non-volatile memory cells in the plurality of analog neural non-volatile memory cells with a level corresponding to the largest cell current among the N levels, wherein each of the analog neural non-volatile memory cells in the second group is adjacent within the array to one or more of the analog neural non-volatile memory cells in the first group, thereby generating the highest electrical field possible among all combinations of the N levels in adjacent cells;
• measuring a current drawn by the first group and the second group of analog neural non-volatile memory cells;
• comparing the measured current to a target value;
• and
• identifying the plurality of analog neural non-volatile memory cells as bad if the difference between the measured value and the target value exceeds a threshold.