Vector-by-matrix-multiplication array utilizing analog outputs

A system comprising:

• a vector by matrix multiplication array comprising a plurality of non-volatile memory cells arranged in rows and columns;
• and
• an output circuit to receive a respective neuron current from the respective columns of the vector by matrix multiplication array and to generate a respective output voltage, the output circuit comprising:
• a neuron scalar to generate a scaled current from the received respective neuron current;
• an activation circuit to perform an activation function on the scaled current to generate an activation current;
• and
• a logarithmic current-to-voltage converter to convert the activation current into the respective output voltage according to a logarithmic function of the activation current, the logarithmic current-to-voltage converter comprising:
• a reference memory cell comprising a bit line terminal coupled to receive the activation current, a source line terminal coupled to ground, and a control gate terminal;
• an operational amplifier comprising an inverting terminal for receiving the activation current, a noninverting terminal for receiving a reference voltage, and an output to provide the respective output voltage, wherein the output is coupled to the control gate terminal of the reference memory cell.

A system comprising:

• a vector by matrix multiplication array comprising a plurality of non-volatile memory cells arranged in rows and columns;
• and
• an output circuit to receive a respective neuron current from respective columns of the vector by matrix multiplication array and to generate a respective output voltage, the output circuit comprising:
• a neuron scalar to generate a scaled current from the received respective neuron current;
• a logarithmic current-to-voltage converter to convert the scaled current into a converted voltage according to a logarithmic function of the scaled current, the logarithmic current-to-voltage converter comprising:
• a reference memory cell comprising a bit line terminal coupled to receive the scaled current, a source line terminal coupled to ground, and a control gate terminal;
• an operational amplifier comprising an inverting terminal for receiving the scaled current, a noninverting terminal for receiving a reference voltage, and an output to provide the respective output voltage, wherein the output is coupled to the control gate terminal of the reference memory cell;
• and
• an activation circuit to perform an activation function on the converted voltage to generate the respective output voltage.