Hardware accelerator with configurable tensor operation pipeline

A hardware accelerator for use with a processor of a computing system, comprising:

• a configurable plurality of fixed tensor operation logic units configured to perform a plurality of predetermined types of tensor operations;
• and
• tensor operation pipeline logic configured to:
• receive from the processor a pipeline command including a software-defined tensor operation pipeline definition defining a plurality of tensor operation stages in a tensor operation pipeline and associated predetermined tensor operations to be performed at each of the defined tensor operation stages, wherein:
• each of the tensor operation stages specifies a corresponding one of the configurable plurality of fixed tensor operation logic units;
• the tensor operation stages are in a predetermined order defined by an on-chip hardware layout, and individual fixed tensor operation logic units can be turned on or off by command;
• and
• at least one of the tensor operation stages includes a lookup table logic unit as the fixed tensor operation logic unit for that tensor operation stage;
• receive tensor data to be computed by the tensor operation pipeline, and
• implement the tensor operation pipeline to perform the tensor operations in each of the tensor operation stages on the tensor data, to thereby produce a tensor operation pipeline result for the tensor data, and output the tensor operation pipeline result to the processor.

A computing system comprising:

• a processor, and
• a hardware accelerator communicatively coupled to the processor, the hardware accelerator including a configurable plurality of fixed tensor operation units configured to perform a plurality of predetermined types of tensor operations, wherein
• the hardware accelerator is configured to receive from the processor a pipeline command including a software-defined tensor operation pipeline definition defining a plurality of tensor operation stages in a tensor operation pipeline and associated predetermined tensor operations to be performed at each of the defined tensor operation stages,
• each of the tensor operation stages specifies a corresponding one of the configurable plurality of fixed tensor operation logic units,
• the tensor operation stages are in a predetermined order defined by an on-chip hardware layout, and individual fixed tensor operation logic units can be turned on or off by command,
• at least one of the tensor operation stages includes a lookup table logic unit as the fixed tensor operation logic unit for that tensor operation stage,
• the hardware accelerator is further configured to receive tensor data to be computed by the tensor operation pipeline, and
• in response to receiving the tensor pipeline command and the tensor data, the hardware accelerator is configured to implement the tensor operation pipeline to perform the tensor operations in each of the tensor operation stages on the tensor data, to thereby produce a tensor operation pipeline result for the tensor data, and output the tensor operation pipeline result to the processor.