Input/output (I/O) register reflected in CPU memory

A system comprising:

• a host processor;
• a main memory connected to the host processor;
• and
• an input/output (I/O) controller coupled to the host processor via an I/O bus, the I/O controller having a memory;
• wherein the host processor is configured to execute instructions to:
• configure a queue for the I/O controller, the queue located in the memory of the I/O controller;
• specify a memory address for updates by the I/O controller, the memory address located in the main memory;
• submit an entry in the queue for a command to be executed by the I/O controller;
• and
• read the memory address, instead of a hardware register located in the I/O controller, to determine that the command has been executed by the I/O controller, wherein the I/O controller is configured to, in response to executing the command, write contents of the hardware register into the memory address.

A non-transitory computer-readable medium comprising instructions that, when executed by a host processor, cause the host processor to perform operations comprising:

• configuring, by the host processor, a queue for an input/output (I/O) controller, the queue located in a memory of the I/O controller;
• specifying, by the host processor, a memory address for updates by the I/O controller, the memory address located in a main memory connected to the host processor;
• submitting, by the host processor, an entry in the queue for a command to be executed by the I/O controller;
• and
• reading, by the host processor, the memory address, instead of a hardware register located in the I/O controller, to determine that the command has been executed by the I/O controller, wherein the I/O controller is configured to, in response to executing the command, write contents of the hardware register into the memory address.