Maintenance operations in a DRAM
AssigneeRambus Inc.
InventorsFrederick A. Ware, Robert E. Palmer, John W. Poulton
Life of this patent
Estimating the term…
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AssigneeRambus Inc.
InventorsFrederick A. Ware, Robert E. Palmer, John W. Poulton
Estimating the term…
A system includes a memory controller and a memory device having a command interface, refresh circuitry, control logic, and a plurality of memory banks, each with a plurality of rows of memory cells. The command interface is operable to receive a refresh command from a memory controller and the refresh circuitry is configured to perform one or more refresh operations to refresh data stored in at least one bank of the plurality of memory banks during a refresh time interval in response to the refresh command from the memory controller. The control logic is to configure the command interface to enter a calibration mode during the refresh time interval, and the command interface is configured to perform a calibration operation in the calibration mode during the refresh time interval.
A memory controller to control a dynamic random access memory (DRAM) device that includes a data interface to receive data, and DRAM memory cells, the memory controller comprising:
A method of operation of a memory controller to control a dynamic random access memory (DRAM) device that includes a data interface to receive data, and DRAM memory cells, the method comprising:
A memory controller to control a dynamic random access memory (DRAM) device that includes a data interface to receive data, and DRAM memory cells, the memory controller comprising:
Dependencies are inferred from the claim text.