Power-aware transmission of quantum control signals

A quantum computing apparatus comprising a classical interface and a quantum processing unit (QPU), wherein the classical interface comprises a central processing unit (CPU) and a programable logic unit,

• wherein the CPU is configured to:
• receive a digital control signal describing a quantum circuit to be performed by the QPU;
• compress the digital control signal using a preselected compression scheme;
• generate a sequence staggering configuration indicating one or more delays to be applied to transmission of the compressed digital control signal and a map indicating a number of bits to be transmitted over each of the plurality of communication channels;
• and
• output, to the programable logic unit, the compressed digital control signal, the sequence staggering configuration and the map,
• and wherein the programable logic unit is configured to:
• split the compressed digital control signal into one or more sub-streams using the map and sequence staggering configuration;
• transmit, to the QPU, the one or more sub-streams, wherein the sub-streams are transmitted with the one or more delays.

A non-transitory computer-readable medium comprising instructions which, when executed by a computing computer comprising a quantum processing unit (QPU) and a classical interface, cause the quantum computing apparatus to:

• receive, at a central processing unit (CPU) of the classical interface, a digital control signal describing a quantum circuit to be performed by the QPU;
• compress, at the CPU, the digital control signal using a preselected compression scheme;
• generate, at the CPU, a sequence staggering configuration indicating one or more delays to be applied to transmission of the compressed digital control signal and a map indicating a number of bits to be transmitted over each of the plurality of communication channels;
• output, from the CPU to a programable logic unit of the classical interface, the compressed digital control signal, the sequence staggering configuration and the map;
• split, at the programable logic unit, the compressed digital control signal into one or more sub-streams using the map and sequence staggering configuration;
• and,
• transmit, from the programable logic unit to the QPU, the one or more sub-streams, wherein the sub-streams are transmitted with the one or more delays.