Defect detecting system of automotive apparatus

A defect detecting system of an automotive apparatus, the defect detecting system comprising:

• a digital function block comprising:
• a memory device configured to store data,
• a first Built-In Self Test (BIST) configured to detect a first defect in the memory device, and
• a comparison parity generator configured to generate a comparison parity for the data,
• wherein the digital function block is configured to operate at a first power supply voltage;
• a level shift block comprising:
• a first path configured to convert the data based on the first power supply voltage into a level based on a second power supply voltage that is different than the first power supply voltage and transmit the data, and
• a second path configured to convert the comparison parity based on the first power supply voltage into a level based on the second power supply voltage, and transmit the comparison parity;
• and
• an analog function block configured to operate at the second power supply voltage, wherein the analog function block is configured to:
• generate a verification parity using the level-converted data,
• receive a level-converted comparison parity,
• compare the comparison parity with the verification parity, and
• detect whether there is a second defect in either or both of the first path and the second path.

A defect detecting system of an automotive apparatus, the defect detecting system comprising:

• a digital function block configured to operate at a first power supply voltage and comprising a memory device configured to store data;
• a first level shift block connected to the digital function block by a first path and configured to convert the data based on the first power supply voltage to a level based on a second power supply voltage that is different than the first power supply voltage;
• an analog function block configured to operate at the second power supply voltage, the analog function block being connected to the first level shift block by the first path and comprising a verification parity generator configured to generate a verification parity from the level-converted data;
• and
• a second level shift block connected between the analog function block and the digital function block by a second path, configured to convert the verification parity based on the second power supply voltage to a level based on the first power supply voltage,
• wherein the digital function block is configured to detect, based on the verification parity, a first defect in the first path or an error in the data.