Package comprising a substrate with post interconnects and a solder resist layer having a cavity

A package comprising:

• a first substrate comprising:
• at least one first dielectric layer;
• a first plurality of interconnects;
• and
• a first solder resist layer;
• a first integrated device coupled to the first substrate;
• a second substrate comprising:
• a first surface and a second surface;
• at least one second dielectric layer;
• a second plurality of interconnects, wherein the second plurality of interconnects comprises a plurality of post interconnects;
• and
• a second solder resist layer coupled to the second surface of the second substrate,
• wherein the second solder resist layer comprises:
• a first solder resist layer portion comprising a first thickness, wherein the first solder resist layer portion vertically overlaps with the first integrated device;
• and
• a second solder resist layer portion comprising a second thickness that is greater than the first thickness, wherein the second solder resist layer portion is coupled to and touching a side portion of each post interconnect from the plurality of post interconnects,
• wherein the second surface of the second substrate faces in the direction of the first substrate,
• wherein the second solder resist layer includes a cavity, and
• wherein the cavity is located laterally to the second solder resist layer portion and a post interconnect from the plurality of post interconnects,
• wherein the cavity is located vertically between the first integrated device and the second solder resist layer, and
• wherein the second solder resist layer directly touches the at least one second dielectric layer of the second substrate,
• a plurality of ball interconnects and a plurality of solder interconnects coupled to the first substrate and the second substrate,
• wherein the plurality of ball interconnects and the plurality of solder interconnects are located between the first substrate and the second substrate,
• wherein the plurality of ball interconnects and the plurality of solder interconnects are configured to couple the first substrate to the second substrate, and
• wherein a first solder interconnect from the plurality of solder interconnects directly touches (i) a ball interconnect from the plurality of ball interconnects, (ii) an interconnect from the first plurality of interconnects of the first substrate, (iii) the post interconnect from the plurality of post interconnects of the second substrate, (iv) a first solder resist layer of the first substrate and (v) the second solder resist layer of the second substrate, and
• an encapsulation layer located between the first substrate and the second substrate,
• wherein the encapsulation layer directly touches the first solder resist layer of the first substrate and the second solder resist layer of the second substrate, and
• wherein the encapsulation layer is a different material from the first solder resist layer and the second solder resist layer.