Semiconductor device assemblies with cavity-embedded cubes and logic-supporting interposers

A semiconductor device assembly, comprising:

• a package substrate including:
• an upper surface having a plurality of internal contacts,
• a lower surface having a plurality of external contacts electrically coupled to the plurality of internal contacts, and
• a plurality of cavities extending into the package substrate from the upper surface, wherein the plurality of internal contacts of the upper surface are spaced laterally away from the plurality of cavities;
• a plurality of stacks of first semiconductor devices, each stack of the plurality of stacks of first semiconductor devices being disposed in a corresponding cavity of the plurality of cavities, an uppermost first semiconductor device of each stack having a plurality of stack contacts substantially coplanar with the plurality of internal contacts;
• an interposer disposed over the upper surface of the package substrate, over the uppermost first semiconductor device of each stack, and over the cavity plurality of cavities, the interposer including:
• a bottom surface having a first plurality of lower contacts electrically coupled to the plurality of stack contacts of each of the plurality of stacks of first semiconductor devices and a second plurality of lower contacts electrically coupled to the plurality of internal contacts, and
• a top surface having a plurality of upper contacts coupled to the first and second pluralities of lower contacts;
• a second semiconductor device disposed over the top surface of the interposer and including a plurality of die contacts electrically coupled to the plurality of upper contacts;
• and
• an encapsulant material that at least partially encapsulates the interposer and the second semiconductor device, a bottom surface of the encapsulant material being in contact with the upper surface of the package substrate.

A method of making a semiconductor device assembly, comprising:

• providing a package substrate including an upper surface having a plurality of internal contacts, a lower surface having a plurality of external contacts electrically coupled to the plurality of internal contacts, and a cavity extending into the package substrate from the upper surface, wherein the plurality of internal contacts of the upper surface are spaced laterally away from the cavity;
• disposing a stack of first semiconductor devices in the cavity, an uppermost first semiconductor device of the stack of first semiconductor devices having a plurality of stack contacts substantially coplanar with the plurality of internal contacts;
• disposing an interposer over the upper surface of the package substrate, over the uppermost first semiconductor device, and over the cavity, the interposer including (i) a bottom surface having a first plurality of lower contacts and a second plurality of lower contacts and (ii) a top surface having a plurality of upper contacts coupled to the first and second pluralities of lower contacts;
• electrically coupling the first plurality of lower contacts to the plurality of internal contacts and the second plurality of lower contacts to the plurality of stack contacts;
• disposing a second semiconductor device over the top surface of the interposer;
• electrically coupling a plurality of die contacts of the second semiconductor device to the plurality of upper contacts of the interposer;
• and
• at least partially encapsulating the interposer and the second semiconductor device with an encapsulant material, a bottom surface of the encapsulant material being in contact with the upper surface of the package substrate.