Semiconductor package
AssigneeSamsung Electronics Co., Ltd.
InventorGeunwoo Kim
Life of this patent
Estimating the term…
Abstract
A semiconductor package includes a semiconductor chip including a semiconductor substrate having a first surface and a second surface opposite to the first surface, a chip pad located on the first surface and including a conductive layer, a support pad positioned on the first surface, spaced apart from the chip pad and including an insulating layer, a support bump connected to the support pad, a wiring substrate disposed to face the semiconductor substrate, a support bonding on trace (BOT) pad disposed on the wiring substrate and bonded to the support bump, and a dummy area disposed on the wiring substrate and spaced apart from the support BOT pad.
Claims20
A semiconductor package comprising:
- a semiconductor chip including a semiconductor substrate having a first surface and a second surface opposite to the first surface;
- a chip pad disposed on the first surface of the semiconductor substrate and comprising a conductive layer;
- a support pad disposed on the first surface of the semiconductor substrate, spaced apart from the chip pad, and comprising an insulating layer;
- a support bump connected to the support pad;
- a wiring substrate disposed to face the semiconductor substrate;
- a support bonding on trace (BOT) pad disposed on the wiring substrate and bonded to the support bump;
- and
- a dummy area disposed on the wiring substrate and spaced apart from the support BOT pad.
A semiconductor package comprising:
- a semiconductor chip including a semiconductor substrate having a first surface and a second surface opposite to the first surface;
- a chip pad disposed on the first surface of the semiconductor substrate and comprising a conductive layer;
- a support pad disposed on the first surface of the semiconductor substrate, spaced apart from the chip pad, and comprising an insulating layer;
- a conductive bump connected to the chip pad;
- a support bump connected to the support pad;
- a wiring substrate disposed to face the semiconductor substrate;
- a wiring bonding on trace (BOT) pad disposed on the wiring substrate and bonded to the conductive bump;
- a support BOT pad disposed on the wiring substrate and bonded to the support bump;
- and
- a dummy area spaced apart from the support BOT pad on the wiring substrate and comprising a conductive layer,
- wherein the conductive bump is electrically connected to a wiring layer formed on the wiring substrate, and the support bump is not electrically connected to the wiring layer.
A semiconductor package comprising:
- a semiconductor chip including a semiconductor substrate having a first surface and a second surface opposite to the first surface;
- a chip pad disposed on the first surface of the semiconductor substrate and comprising a conductive layer;
- a support pad disposed on the first surface of the semiconductor substrate, spaced apart from the chip pad, and comprising an insulating layer;
- a conductive bump connected to the chip pad;
- a support bump connected to the support pad;
- a wiring substrate disposed to face the semiconductor substrate;
- a wiring bonding on trace (BOT) pad disposed on the wiring substrate and bonded to the conductive bump;
- a support BOT pad disposed on the wiring substrate and bonded to the support bump;
- and
- a dummy area disposed on the wiring substrate and spaced apart from the support BOT pad,
- wherein the support BOT pad is part of a first linear trace pattern extending in a first direction in a plane on the wiring substrate, and
- wherein the dummy area is spaced apart from the first linear trace pattern and surrounds the first linear trace pattern in a plane on the wiring substrate.
Dependencies are inferred from the claim text.