US 12,666,935 B2Granted

Implantation through an etch stop layer

AssigneeIntel Corporation

InventorsMoshe Dolejsi, Harish Ganapathy, Travis W. Lajoie, Deepyanti Taneja, Huiying Liu, Cheng Tan, Timothy Jen, Van H. Le, Abhishek A. Sharma

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Abstract

An integrated circuit includes a first layer comprising dielectric material. One or both of an interconnect feature and a device are within the dielectric material of the first layer. The integrated circuit further includes a second layer above the first layer, where the second layer includes dielectric material. A third layer is between the first layer and the second layer. In an example, the third layer can be, for example, an etch stop layer or a liner layer or barrier layer. In an example, an impurity is within the first layer and the third layer. In an example, the impurity has a detectable implant depth profile such that a first distribution of the impurity is within the first layer and a second distribution of the impurity is within the third layer.

Claims23

Dependent claims

An integrated circuit comprising:

a first layer comprising dielectric material, and one or both of an interconnect feature and a device within the dielectric material of the first layer;
a second layer above the first layer, the second layer comprising dielectric material, and one or both of an interconnect feature and a device within the dielectric material of the second layer;
and
a third layer between the first layer and the second layer, the third layer having a thickness between the first and second layers in the range of 0.5 to 50 nanometers;
and
an impurity within the first layer and the third layer, the impurity having a detectable implant depth profile such that a first distribution of the impurity is within the first layer and a second distribution of the impurity is within the third layer,
wherein the dielectric material of the first layer comprises a first section and a second section, the first section laterally adjacent to the second section within the dielectric material of the first layer, the impurity within the first section is at a first average depth from a surface of the third layer, and the impurity within the second section is at a second average depth from the surface of the third layer, wherein the first average depth is more than the second average depth.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/656,366Filed 24 Mar 2022
Published: US 2023/0307291 A128 Sep 2023
Granted: 23 Jun 2026
Term ends: Not estimatedThe source records don’t support an estimate.

Classification8 codes

H10W 20/074
Of dielectric parts thereof: of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or…
H10B 12/033
Making the capacitor or connections thereto: the capacitor extending over the transistor
H10B 12/05
For one transistor one-capacitor [1T-1C] memory cells: making the transistor
H10W 20/051
By introducing additional elements therein: by ion implantation