US 12,666,712 B2Granted

Integrated circuit and method of forming the same

AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.

InventorsHui-Zhong Zhuang, Johnny Chiahoa Li, Tzu-Ying Lin, Jia-Hong Gao, Jung-Chan Yang, Jerry Chang Jui Kao

Life of this patent

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Abstract

A flip-flop includes a first, second, third and a fourth active region extending in a first direction, and being on a first level of a substrate. The first active region corresponds to a first set of transistors of a first type. The second active region corresponds to a second set of transistors of a second type different from the first type. The third active region corresponds to a third set of transistors of the second type. The fourth active region corresponds to a fourth set of transistors of the first type. The flip-flop further includes a first gate structure extending in the second direction, overlapping at least the second active region and the third active region, and being on a second level different from the first level. The first gate structure is configured to receive a first clock signal.

Claims20

Dependent claims

A flip-flop comprising:

a first active region extending in a first direction, and being on a first level of a substrate, the first active region corresponding to a first set of transistors of a first type;
a second active region extending in the first direction, being on the first level, and being separated from the first active region in a second direction different from the first direction, the second active region corresponding to a second set of transistors of a second type different from the first type;
a third active region extending in the first direction, being on the first level, and being separated from the first active region and the second active region in the second direction, the third active region corresponding to a third set of transistors of the second type;
a fourth active region extending in the first direction, being on the first level, and being separated from the first active region, the second active region and the third active region in the second direction, the fourth active region corresponding to a fourth set of transistors of the first type;
a first gate structure extending in the second direction, overlapping the second active region, the third active region and the fourth active region, and being on a second level different from the first level, the first gate structure being configured to receive a first clock signal;
a second gate structure extending in the second direction, overlapping the first active region, and being on the second level, the second gate structure being configured to receive a second clock signal inverted from the first clock signal, and being separated from the first gate structure in the second direction;
a third gate structure extending in the second direction, overlapping the second active region, the third active region and the fourth active region, and being on the second level, the third gate structure being configured to receive the second clock signal, the third gate structure being separated from the first gate structure in the first direction;
and
a fourth gate structure extending in the second direction, overlapping the first active region, and being on the second level, the fourth gate structure being configured to receive the first clock signal, and being separated from the third gate structure in the second direction;
wherein the first gate structure and the second gate structure are aligned with each other along a first common axis that extends in the second direction, and
the third gate structure and the fourth gate structure are aligned with each other along a second common axis that extends in the second direction.

8 more elements

A flip-flop, comprising:

a first active region extending in a first direction, and being on a first level, the first active region corresponding to a first row of a first set of transistors of a first type, the first active region comprising:
a first portion of the first active region having a first width in a second direction different from the first direction;
and
a second portion of the first active region having a second width in the second direction, the second width being different from the first width;
a second active region extending in the first direction, being on the first level, and being separated from the first active region in the second direction, the second active region corresponding to a second row of a second set of transistors of a second type different from the first type, the second active region comprising:
a first portion of the second active region having the first width in the second direction;
and
a second portion of the second active region having the second width in the second direction;
and
a first dummy gate extending in the second direction, being located on a second level different from the first level, and the first dummy gate separating at least the first portion of the first active region from the second portion of the first active region, or the first portion of the second active region from the second portion of the second active region.

7 more elements

A flip-flop comprising:

a first active region extending in a first direction, and being on a first level of a substrate, the first active region corresponding to a first set of transistors of a first type;
a second active region extending in the first direction, being on the first level, and being separated from the first active region in a second direction different from the first direction, the second active region corresponding to a second set of transistors of a second type different from the first type;
a third active region extending in the first direction, being on the first level, and being separated from the first active region and the second active region in the second direction, the third active region corresponding to a third set of transistors of the second type;
a fourth active region extending in the first direction, being on the first level, and being separated from the first active region, the second active region and the third active region in the second direction, the fourth active region corresponding to a fourth set of transistors of the first type;
a first gate structure extending in the second direction, overlapping the first active region, the second active region, the third active region and the fourth active region, and being on a second level different from the first level, the first gate structure being configured to receive a first clock signal;
and
a second gate structure extending in the second direction, overlapping the first active region, the second active region, the third active region and the fourth active region, and being on the second level, the second gate structure being configured to receive a second clock signal inverted from the first clock signal, the second gate structure being separated from the first gate structure in the first direction.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 18/314,536Filed 9 May 2023 · us provisional application
Priority: 27 Jul 2022
Published: US 2024/0038762 A11 Feb 2024
Granted: 23 Jun 2026
Term ends: Not estimatedThe source records don’t support an estimate.

Classification18 codes

H10D 84/907
Comprising field effect technology: cMOS gate arrays
H03K 3/037
By the use of logic circuits, with internal or external positive feedback: bistable circuits
H03K 3/0372
Bistable circuits: of the primary-secondary type
H03K 3/35625
Of the primary-secondary type: using complementary field-effect transistors