Large dimension metal gate field-effect transistor (FET) with metal gate dummy structures

A method comprising:

• forming an active region;
• and
• forming a gate stack on the active region, the gate stack comprising:
• at least one gate dielectric layer disposed on the active region;
• and
• a metal gate structure disposed on the at least one gate dielectric layer, the metal gate structure comprising:
• a metal gate layer comprising a first material;
• and
• at least one dummy structure surrounded by the metal gate layer, the at least one dummy structure extending vertically through an entire thickness of the metal gate structure and comprising a second material, wherein the second material is different from the first material.

A field-effect transistor (FET) comprising:

• a semiconductor substrate having an active region, the active region including a source region and a drain region separated by a channel region;
• and
• a gate stack disposed over the channel region, the gate stack comprising:
• at least one gate dielectric layer disposed on the active region;
• and
• a metal gate structure disposed on the at least one gate dielectric layer, the metal gate structure comprising:
• a metal gate layer comprising a first material;
• and
• a plurality of dummy structures surrounded by the metal gate layer, the plurality of dummy structures forming a dummy pattern and extending vertically through an entire thickness of the metal gate electrode, wherein the dummy structures comprise a second material that is different from the first material.