Enabling anneal for reliability improvement and multi-VT with interfacial layer regrowth suppression
AssigneeInternational Business Machines Corporation
InventorsRuqiang Bao, Huiming Bu
Life of this patent
Estimating the term…
Abstract
A method for fabricating a semiconductor device includes forming an interfacial layer and a dielectric layer on a base structure and around channels of a first gate-all-around field-effect transistor (GAA FET) device within a first region and a second GAA FET device within a second region, forming at least a scavenging metal layer in the first and second regions, and performing an anneal process after forming at least one cap layer.
Claims19
A semiconductor device providing a multiple threshold voltage (Vt) scheme, comprising:
- a first gate-all-around field-effect transistor (GAA FET) device having a first Vt disposed on a first region of a substrate, the first GAA FET device including:
- a plurality of first channels;
- an interfacial layer around each of the plurality of the first channels;
- a dielectric layer around the interfacial layer;
- a dipole layer around the plurality of first channels, between the plurality of first channels and the dielectric laver;
- and
- a first work function metal between each adjacent pair of the plurality of first channels;
- and
- a second GAA FET device having a second Vt different from the first Vt disposed on a second region of the substrate, the second GAA FET device including:
- a plurality of second channels with no dipole layer around them;
- a second work function metal between each adjacent pair of the plurality of second channels;
- and
- the first work function metal on the second work function metal.
A semiconductor device providing a multiple threshold voltage (Vt) scheme, comprising;
- a first gate-all-around field-effect transistor (GAA FET) device disposed on a base structure in a first region and associated with a first Vt, the first GAA FET device including:
- a plurality of first channels;
- an interfacial layer around each of the plurality of the first channels;
- a dielectric layer around the interfacial layer;
- a dipole layer around the plurality of first channels, between the plurality of first channels and the dielectric layer;
- and
- a first work function metal pinching off gaps between the plurality of first channels;
- a second GAA FET device disposed on the base structure in a second region and associated with a second Vt, the second GAA FET device including:
- a plurality of second channels with no dipole layer around them;
- a second work function metal pinching off gaps between the plurality of second channels;
- and
- the first work function metal on the second work function metal;
- and
- a gate electrode on the first work function metal.
A semiconductor device providing a multiple threshold voltage (Vt) scheme, comprising:
- a first gate-all-around field-effect transistor (GAA FET) device disposed on a base structure in a first region and associated with a first Vt, the first GAA FET device including:
- a plurality of first channels;
- an interfacial layer around each of the plurality of first channels;
- a dielectric layer around the interfacial layer;
- a dipole layer around the plurality of first channels, between the plurality of first channels and the dielectric layer;
- a first barrier layer on the dipole layer;
- a scavenging metal layer on the first barrier layer;
- a wetting layer on the scavenging metal layer around the plurality of first channels;
- and
- a first work function metal between each adjacent pair of the plurality of first channels;
- and
- a second GAA FET device disposed on the base structure in a second region and associated with a second Vt, the second GAA FET device including:
- a plurality of second channels with no dipole layer around them;
- a second barrier layer on the plurality of second channels;
- the scavenging metal layer on the second barrier layer;
- the wetting layer on the scavenging metal layer;
- a gate electrode on the wetting layer;
- a second work function metal between each adjacent pair of the plurality of second channels;
- and
- the first work function metal on the second work function metal.
Dependencies are inferred from the claim text.