US 12,666,612 B2 · Asymmetric single-channel floating gate memristor

Abstract

A single-channel, single-poly floating gate (EEPROM-type) memristor including asymmetric source/drain-to-gate coupling and an asymmetric channel doping pattern. Asymmetric source/drain-to-gate coupling is achieved by configuring the drain, source and floating gate such that the gate-to-drain capacitance is greater than the gate-to-source capacitance. The asymmetric channel doping pattern is implemented by forming different drain-side and source-side doping portions (i.e., different N-type or P-type implant configurations and/or positions). The asymmetric channel doping pattern is preferably formed using standard CMOS implants (e.g., NLDD and P-type pocket implants). Multiple N-type and P-type implants may be selectively positioned to achieve a desired balance between program/erase speeds, reverse (read direction) threshold voltage and immunity to read-disturb and over-erase. A drain-side diode may be additionally used to suppress over-erase. A memory circuit including multiple two-terminal memristors disposed in a cross-point array is disclosed, which can be utilized, e.g., in a neuromorphic circuit.

Claims19

Dependent claims

A two-terminal memristor comprising:

a substrate having an upper surface and including a drain region and a source region separated by a channel region;
a gate oxide layer disposed on the upper surface;
a single-piece, integral floating polycrystalline silicon structure disposed on the gate oxide layer and including a first poly portion disposed over the drain region, a second poly portion disposed over the source region and a third poly portion connected between the first and second poly portions and extending over the channel region;
and
an asymmetric channel doping pattern including at least two implants asymmetrically disposed in the channel region between the drain region and the source region,
wherein the single-piece, integral floating polycrystalline silicon structure, the drain region and the source region are configured to generate asymmetric source/drain-to-gate coupling such that a gate-to-drain capacitance generated between the first poly portion and the drain region is greater than a gate-to-source capacitance generated between the second poly portion and the source region, and
wherein said at least two implants comprises at least one N-type dopant implant and at least one P-type dopant implant.

4 more elements

A memory circuit comprising a plurality of two-terminal memristors fabricated on a semiconductor substrate and disposed in a cross-point array, each said memristor having a first terminal connected to an associated first line and a second terminal connected to an associated second line, wherein said each memristor comprises:

a drain region and a source region formed in the substrate and separated by a channel region;
a single-piece, integral floating polycrystalline silicon structure including a first poly portion disposed over the drain region, a second poly portion disposed over the source region and a third poly portion connected between the first and second poly portions and extending over the channel region;
and
an asymmetric channel doping pattern including at least two implants asymmetrically disposed in the channel region between the drain region and the source region,
wherein the single-piece, integral floating polycrystalline silicon structure, the drain region and the source region are configured to generate asymmetric source/drain-to-gate coupling such that a gate-to-drain capacitance generated between the first poly portion and the drain region is greater than a gate-to-source capacitance generated between the second poly portion and the source region, and
wherein said at least two implants comprises at least one N-type dopant implant and at least one P-type dopant implant.

3 more elements

Dependencies are inferred from the claim text.

Asymmetric single-channel floating gate memristor

Life of this patent

Asymmetric single-channel floating gate memristor

Life of this patent

Abstract

Claims19