Thermal conduction—electrical conduction isolated circuit board with ceramic substrate and power transistor embedded

A thermal conduction-electrical conduction isolated printed circuit board with a ceramic substrate and a power transistor embedded, comprising:

• a dielectric material layer comprising a first upper surface and a first lower surface opposite the first upper surface, the dielectric material layer being formed with at least one via hole running through the first upper surface and the first lower surface;
• at least one heat-dissipating ceramic block correspondingly embedded in the via hole, comprising a second upper surface and a second lower surface, wherein the heat-dissipating ceramic block has a thermal conductivity higher than that of the dielectric material layer and a thickness less that of the dielectric material layer;
• at least one securing portion which secures the embedded heat-dissipating ceramic block in the via hole of the dielectric material layer such that the second lower surface corresponds to the first lower surface;
• a stepped metal electrode layer thermally conductively provided on the second upper surface, the stepped metal electrode layer at least comprising one of a source connecting pin or a drain connecting pin, the source connecting pin being partitioned into a thin pad portion and a source connecting portion extending from the thin pad portion, the drain connecting pin being partitioned into a thin pad portion and a drain connecting portion extending from the thin pad portion;
• a power transistor electrically and thermally conductively mounted on the stepped metal electrode layer, the power transistor at least comprising a source, a gate, and a drain, wherein the source is electrically conductively connected to the source connecting pin, the drain is electrically conductively connected to the drain connecting pin;
• wherein alternatively, the stepped metal electrode layer comprises the other one of the source connecting pin or the drain connecting pin, and a gate connecting pin, the source connecting pin being electrically connected to the source, the drain connecting pin being electrically connected to the drain, the gate connecting pin being electrically connected to the gate, wherein the drain connecting pin at least comprises a drain connecting portion, the source connecting pin at least comprises a source connecting portion, and the gate connecting pin at least comprises a gate connecting portion;
• and a dielectric material packaging filling the via hole, wherein the dielectric material packaging encapsulates the second upper surface, the thin pad portion, and the power transistor, whereby to form a third upper surface flush with the first upper surface, and the third upper surface is configured to at least partially expose the source connecting portion of the source connecting pin, the drain connecting portion of the drain connecting pin, and the gate connecting portion of the gate connecting pin, respectively.