Semiconductor devices with power gating

A semiconductor device comprising:

• a retention circuit configured to retain stored data during a power gating operation;
• a non-retention circuit that loses stored data during the power gating operation;
• a clock management unit (CMU) configured to provide a first operation clock to the retention circuit, provide a second operation clock to the non-retention circuit, and output a response signal indicating that the first and second operation clocks have been outputted;
• a power management unit (PMU) configured to:
• provide, to the CMU, a reference clock used by the CMU to generate the first and second operation clocks;
• output a first isolation signal that permits an output of the CMU to be transmitted;
• and
• output a second isolation signal that permits outputs of each of the retention circuit and the non-retention circuit to be transmitted;
• and
• a first logic gate configured to perform a first logical operation on the response signal output from the CMU and the first isolation signal, and provide a result of the first logical operation to the PMU.

A method of operating a semiconductor device, wherein the semiconductor device includes:

• a retention circuit configured to retain stored data during a power gating operation;
• a non-retention circuit that loses stored data during the power gating operation;
• a clock management unit (CMU) configured to provide an operation clock to each of the retention circuit and the non-retention circuit;
• and
• a power management unit (PMU) configured to provide, to the CMU, a reference clock used by the CMU to generate the operation clock, wherein the method comprises:
• based on the power gating operation ending, outputting, by the PMU, the reference clock;
• outputting, by the PMU, a first isolation signal that permits an output of the CMU to be transmitted;
• outputting, by the PMU, to the CMU, a first request signal requesting the CMU to provide the operation clock to each of the retention circuit and the non-retention circuit;
• transmitting, by the CMU, to an external clock source, a second request signal requesting a source clock used by the CMU to generate the operation clock,
• wherein the second request signal is transmitted based on the first request signal and the first isolation signal;
• and
• receiving, by the PMU, from the CMU, a first response signal indicating that the operation clock has been outputted, wherein the first response signal is received based on the first isolation signal.