Clock buffer circuit with improved transition times

An integrated circuit, comprising:

• an inverter circuit having an input node coupled to receive an input signal and an output node configured to provide an output signal corresponding to the inverse of the input signal, wherein the inverter circuit comprises:
• a main inverter stage having a first transistor of a first conductivity type coupled in series with a second transistor of a second conductivity type, wherein control electrodes of the first and second transistors are coupled to the input node and first current electrodes of the first and second transistors are coupled at the output node;
• a first set of additional transistors of the first conductivity type;
• a second set of additional transistors of the second conductivity type;
• a set of switches configured to connect a first transistor of the first set of additional transistors in series with the first transistor for a first time period while connecting a first transistor of the second set of additional transistors in parallel with the second transistor during the first time period;
• and
• a clock buffer circuit, the clock buffer circuit comprising the inverter circuit, and further comprising:
• a set of inverters having an input coupled to the output node of the inverter circuit, and having an output coupled to provide a clock output corresponding to the input signal.

An integrated circuit comprising:

• an inverter circuit having an input node coupled to receive an input signal and an output node configured to provide an output signal, wherein the inverter circuit comprises:
• a first transistor having a first current electrode coupled to a first voltage supply terminal, a control electrode coupled to the input node, and a second current electrode;
• a second transistor having a first current electrode coupled to the second current electrode of the first transistor at a first circuit node, a control electrode coupled to the input node, and a second current electrode coupled to the output node;
• a third transistor having a first current electrode coupled to the first voltage supply terminal, a control electrode coupled to the input node, and a second current electrode;
• a first switch coupled between the first circuit node and the first voltage supply terminal;
• and
• a second switch coupled between the output node and the second current electrode of the third transistor, wherein each of the first and second switches is controlled based on the output signal, and each of the first, second, and third transistors are of a first conductivity type.

An integrated circuit having a clock buffer circuit, the clock buffer circuit comprising:

• an inverter circuit having an input node coupled to receive an input signal and an output node configured to provide an output signal, wherein the inverter circuit comprises:
• a first PMOS transistor having a first current electrode coupled to a first voltage supply terminal, a control electrode coupled to the input node, and a second current electrode;
• a second PMOS transistor having a first current electrode coupled to the second current electrode of the first transistor at a first circuit node, a control electrode coupled to the input node, and a second current electrode coupled to the output node;
• a third PMOS transistor having a first current electrode coupled to the first voltage supply terminal, a control electrode coupled to the input node, and a second current electrode;
• a first switch coupled between the first circuit node and the first voltage supply terminal;
• a second switch coupled between the output node and the second current electrode of the third transistor;
• a fourth NMOS transistor having a first current electrode coupled to a second voltage supply terminal, a control electrode coupled to the input node, and a second current electrode;
• a fifth NMOS transistor having a first current electrode coupled to the second current electrode of the fourth transistor at a second circuit node, a control electrode coupled to the input node, and a second current electrode coupled to the output node;
• a sixth NMOS transistor having a first current electrode coupled to the second voltage supply terminal, a control electrode coupled to the input node, and a second current electrode;
• a third switch coupled between the second circuit node and second first voltage supply terminal;
• and
• a fourth switch coupled between the output node and the second current electrode of the sixth transistor;
• and
• a set of inverters having an input coupled to receive the output signal and an output coupled to provide an output clock.