Intelligent semiconductor switch with quasi-digital current limitation

An integrated circuit comprising:

• a power transistor connected between a supply terminal and an output terminal;
• a control circuit coupled to a gate electrode of the power transistor and configured to apply a gate current to the gate electrode to turn the power transistor on or off;
• a current sensing circuit configured to provide information regarding a load current passing through the power transistor;
• and
• a current control circuit coupled to the gate electrode and configured to generate a discharge current for discharging the gate based on the information regarding the load current and to cause the control circuit to reduce the gate current while the power transistor is switched on,
• wherein the gate current output by the control circuit is reduced in response to the load current exceeding a first threshold value,
• wherein a level of the discharge current is set to a third current level in response to the load current exceeding a third threshold value,
• wherein the level of the discharge current is set to a second current level in response to the load current exceeding a second threshold value, and
• wherein the third current level is greater than the second current level and the second current level is greater than a load current level.

A method comprising:

• generating a gate current;
• switching on a power transistor by applying the gate current to a gate electrode of the power transistor;
• determining information regarding a load current passing through the power transistor;
• and
• controlling, based on the information regarding the load current, the load current by reducing the gate current applied to the gate electrode of the power transistor;
• wherein—in response to the load current exceeding a first threshold value—the gate current is reduced by a specific amount;
• wherein—in response to the load current exceeding a third threshold value—the gate current is further reduced by sinking a discharge current, which has a third current level, from the gate electrode of the power transistor;
• and
• wherein—in response to the load current exceeding a second threshold value—the gate current is reduced by setting the discharge current, which is sunk from the gate electrode, to a second current level.

An integrated circuit comprising:

• a power transistor connected between a supply terminal and an output terminal;
• a control circuit coupled to a gate electrode of the power transistor and configured to apply a gate current to the gate electrode to turn the power transistor on or off,
• a current sensing circuit configured to provide information regarding a load current passing through the power transistor;
• and
• a current control circuit coupled to the gate electrode and configured to generate a discharge current for discharging the gate based on the information regarding the load current,
• wherein a level of the discharge current corresponds to a first current level in response to the load current exceeding a first threshold value,
• wherein the level of the discharge current corresponds to a third current level in response to the load current exceeding a third threshold value, and
• wherein the third current level is so high that the power transistor is completely switched off.