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US 12,665,046 B2Granted
Memory repairs
AssigneeMicron Technology, Inc.
InventorsSukneet S. Basuta, Kenneth M. Curewitz
Life of this patent
Estimating the term…
Abstract
Memory devices can be protected (e.g., repaired) against hard bit errors by remapping logical pages to valid physical addresses and excluding those physical addresses having hard bit errors from being mapped to. The remapping can be done in unit of a finer granularity than a row of memory cells such that those valid memory cells within a row can still be used for the remapping despite that the row may include unusable memory cells.
Claims18
A method, comprising:
- performing a scan operation to determine whether at least a portion of one or more arrays of memory cells of a memory device is bad by:
- writing respective data patterns to a plurality of portions of the array of memory cells;
- reading the data patterns from the plurality of portions;
- and
- determining whether the data patterns read from the plurality of portions match the data patterns written to the plurality of portions to further determine whether the at least the portion of the array of memory cells is bad;
- and
- repairing, responsive to one or more first memory cells of a first row of memory cells of a first array of memory cells being determined to be bad, the array by remapping one or more logical pages to:
- one or more second memory cells of the first row of memory cells;
- and
- one or more additional memory cells.
7 more elements
An apparatus, comprising:
- an array of memory cells;
- sensing circuitry coupled to the array of memory cells;
- and
- a controller coupled to the array of memory cells, the controller configured to;
- remap, in response to one or more first memory cells of a first row of memory cells of the array being determined to be bad, one or more logical pages to:
- one or more second memory cells of the first row of memory cells;
- and
- one or more spare memory cells of a second row of memory cells;
- and
- to access the one or more second memory cells or the one or more spare memory cells mapped to the one or more logical pages:
- activate a first portion of the sensing circuitry coupled to the one or more second memory cells or the one or more spare memory cells;
- and
- maintain a second portion of the sensing circuitry not coupled to the one or more second memory cells or the one or more spare memory cells in a deactivated state.
10 more elements
An apparatus, comprising:
- a memory device comprising a plurality of arrays of memory cells respectively corresponding to a plurality of banks;
- and
- a controller coupled to the array of memory cells, the controller configured to communicate with the memory device according to a double data rate (DDR) protocol;
- wherein the memory device comprises a control logic configured to access the plurality of arrays of memory cells in response to a command from the controller;
- and
- wherein the controller is further configured to remap, in response to one or more first memory cells of a first row of memory cells of a first bank being determined to be bad, one or more logical pages to:
- one or more second memory cells of the first row of memory cells of the first bank;
- and
- one or more third memory cells of a second row of memory cells of a second bank.
6 more elements
An apparatus, comprising:
- a plurality of arrays of memory cells respectively corresponding to a plurality of banks;
- and
- a controller coupled to the array of memory cells, the controller configured to:
- access the array of memory cells according to a double data rate (DDR) protocol;
- remap, in response to one or more first memory cells of a first row of memory cells of a first bank being determined to be bad, one or more logical pages to:
- one or more second memory cells of the first row of memory cells of the first bank;
- and
- one or more third memory cells of a second row of memory cells of a second bank;
- wherein the controller is further configured to store a logical to physical (L2P) table indicative of a mapping between logical addresses and physical addresses of the plurality of arrays;
- and
- wherein the L2P table further comprises a number of bits, each bit of the number of bits indicative of whether a logical address of a respective entry is mapped to different rows of memory cells or not.
8 more elements
Dependencies are inferred from the claim text.