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US 12,665,045 B2Granted
Memory device
AssigneeEtron Technology, Inc.
InventorChun Shiah
Life of this patent
Estimating the term…
Abstract
A memory device is provided. The memory device includes: a package substrate; a memory chip, with chip inputs/outputs (I/Os), and attached to the package substrate; and package terminals, disposed on the package substrate, and having: functional package terminals, connected to the chip I/Os; no-connect (NC) package terminals, arranged among the functional package terminals and not connected to any of the chip I/Os; and redesigned NC package terminals, as additional ones of the NC package terminals but connected to the chip I/Os, so as to be functioned as additional functional package terminals.
Claims17
A memory device, comprising:
- a package substrate;
- a memory chip with chip inputs/outputs (I/Os), the memory chip being attached to the package substrate;
- and
- package terminals disposed on the package substrate, wherein a total amount of the package terminals is in compliance with Joint Electron Device Engineering Council (JEDEC) memory standard, and the package terminals comprise:
- functional terminals connected to the chip I/Os;
- and
- a first no-connect (NC) terminal originally being designated not to connect the chip I/Os according to the JEDEC memory standard, but being redesigned to connect to a first I/O of the chip I/Os, wherein the redesigned first NC terminal is functioned as one additional functional terminal,
- wherein the redesigned first NC terminal is configured for an additional data signal, an additional command signal or an additional address signal, which is different from data signals, command signals or address signals coupled to the functional terminals.
5 more elements
A memory device, comprising:
- a package substrate;
- a memory chip with chip inputs/outputs (I/Os), wherein the memory chip is attached to the package substrate;
- and
- package terminals disposed on the package substrate, wherein a total amount of the package terminals is in compliance with Joint Electron Device Engineering Council (JEDEC) memory standard, and the package terminals comprise:
- functional terminals connected to the chip I/Os;
- and
- a first set of no-connect (NC) terminals originally being designated not to connect the chip I/Os according to the JEDEC memory standard, but being redesigned to connect to a first set I/Os of the chip I/Os,
- wherein the redesigned first set of NC terminals are configured for additional data signals, additional command signals or additional address signals, which are different from data signals, command signals or address signals coupled to the functional terminals.
5 more elements
A memory device, comprising:
- a package substrate;
- a memory chip with chip inputs/outputs (I/Os), the memory chip being attached to the package substrate;
- and
- package terminals disposed on the package substrate, wherein a total amount of the package terminals is in compliance with Joint Electron Device Engineering Council (JEDEC) memory standard, and the package terminals comprise:
- functional terminals connected to the chip I/Os;
- and
- a first no-connect (NC) terminal originally being designated not to connect the chip I/Os according to the JEDEC memory standard, but being redesigned to couple to a thermal via or a thermal plate of the memory chip.
4 more elements
A memory device, comprising:
- a package substrate;
- a memory chip with chip inputs/outputs (I/Os), the memory chip being attached to the package substrate;
- and
- package terminals disposed on the package substrate, wherein a total amount of the package terminals is in compliance with Joint Electron Device Engineering Council (JEDEC) memory standard, and the package terminals comprise:
- functional terminals connected to the chip I/Os;
- and
- a first no-connect (NC) terminal originally being designated not to connect the chip I/Os according to the JEDEC memory standard, but being redesigned to connect to a first I/O of the chip I/Os, wherein the redesigned first NC terminal is functioned as one additional functional terminal,
- wherein the redesigned first NC terminal is connected to an external voltage source, such that a working voltage is supplied to the memory chip through the redesigned first NC terminal and the first I/O of the chip I/Os.
5 more elements
Dependencies are inferred from the claim text.