Semiconductor device and simultaneous block operations method using multiple source lines
AssigneeSK hynix Inc.
InventorsWon Jae Choi, Sung Lae Oh, Jea Won Choi
Life of this patent
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Abstract
A semiconductor device may include a first source line driving circuit that drives a first source line, a second source line driving circuit that drives a second source line, a first memory block including a plurality of first memory strings coupled between the first source line and a plurality of bit lines, respectively, and a second memory block including a plurality of second memory strings coupled between the second source line and the plurality of bit lines, respectively.
Claims20
A semiconductor device comprising:
- a memory array with NAND strings;
- a first source line driving circuit that drives a first source line;
- a second source line driving circuit that drives a second source line;
- a first memory block including a plurality of first memory strings coupled between the first source line and a plurality of bit lines, respectively;
- and
- a second memory block including a plurality of second memory strings coupled between the second source line and the plurality of bit lines, respectively,
- wherein each of the first and second source line driving circuits drives the first and second source lines to different levels, respectively, so that one of the first and second memory blocks performs an erase operation while the other performs a read operation or program operation.
An operation method of a semiconductor device having a memory array with NAND strings, the operation method comprising:
- driving a first source line to a level of an erase voltage;
- driving a second source line to a level of one of a ground voltage and a power supply voltage;
- performing an erase operation on a first memory block coupled to the first source line;
- and
- performing a read operation or a program operation on a second memory block coupled to the second source line while the first memory block performs the erase operation,
- wherein the erase voltage, the ground voltage, and the power supply voltage have different levels from each other.
A semiconductor device comprising:
- a memory array with NAND strings;
- a first source line;
- a second source line;
- a plurality of bit lines;
- a first memory block including a plurality of first memory strings coupled between the first source line and the plurality of bit lines, respectively;
- a second memory block including a plurality of second memory strings coupled between the second source line and the plurality of bit lines, respectively;
- a control circuit configured to simultaneously perform an erase operation on the first memory block, and a read or program operation on the second memory block;
- a first source line driving circuit configured to drive the first source line to an erase voltage;
- and
- a second source line driving circuit configured to drive the second source line to a ground voltage less than the erase voltage.
Dependencies are inferred from the claim text.