US 12,665,012 B2 · Operation method of ferroelectric memory

Abstract

A method of operating a set of ferroelectric memory cells is provided. The method may include, in a first cycle, writing a first data bit to a first ferroelectric memory cell of the set of ferroelectric memory cells. The method may include, in the first cycle, writing a set of sign bits each having a first value to at least one second ferroelectric memory cell of the set of ferroelectric memory cells. The set of sign bits may indicate a polarity of the set of ferroelectric memory cells. The method may include, in a second cycle subsequent to the first cycle, reading the set of sign bits from the at least one second ferroelectric memory cell. The method may include, in the second cycle, performing an error-correction operation on the set of sign bits to determine the first value of the set of sign bits written in the first cycle.

Claims20

Dependent claims

A method of operating a set of ferroelectric memory cells, comprising:

in a first cycle, writing a first data bit to a first ferroelectric memory cell of the set of ferroelectric memory cells;
in the first cycle, writing a set of sign bits each having a first value to at least one second ferroelectric memory cell of the set of ferroelectric memory cells, the set of sign bits indicating a polarity of the at least one second ferroelectric memory cell;
in a second cycle subsequent to the first cycle, reading the set of sign bits from the second ferroelectric memory cell;
and
in the second cycle, performing an error-correction operation on a set of stored bits to determine the first value of the set of sign bits written in the first cycle.

2 more elements

A memory device, comprising:

a set of ferroelectric memory cells;
and
a peripheral circuit coupled to the set of ferroelectric memory cells and configured to:
in a first cycle, write a first data bit to a first ferroelectric memory cell of the set of ferroelectric memory cells;
in the first cycle, write a set of sign bits each having a first value to at least one second ferroelectric memory cell of the set of ferroelectric memory cells, wherein the at least one second ferroelectric memory cell is different from the first ferroelectric memory cell, and wherein the set of sign bits indicates a polarity of the first data bit written in the first cycle;
in a second cycle subsequent to the first cycle, read the set of sign bits from the second ferroelectric memory cell;
and
in the second cycle, perform an error-correction operation on a set of stored bits to determine the first value of the set of sign bits written in the first cycle, wherein the error-correction operation determines the polarity of the first data bit written in the first cycle based on the set of sign bits read in the second cycle.

5 more elements

Dependencies are inferred from the claim text.

Operation method of ferroelectric memory

Life of this patent

Operation method of ferroelectric memory

Life of this patent

Abstract

Claims20