Memory device and operating method thereof
AssigneeSK hynix Inc.
InventorTae Jung Ha
Life of this patent
Estimating the term…
Abstract
Memory devices and operating methods are disclosed. In an embodiment, a memory device may include a memory cell array including a plurality of memory cells, each of the plurality of memory cells configured to store a data value corresponding to read data to be read out through a plurality of conductive lines, and a read circuit connected to the plurality of conductive to generate the read data corresponding to the data value stored in a selected memory cell among the plurality of memory cells based on or according to whether there is a change in a cell current flowing through the selected memory cell during a single read period.
Claims18
A memory device comprising:
- a memory cell array including a plurality of memory cells, each of the plurality of memory cells configured to store a first data value or a second data value corresponding to read data to be read out through a plurality of conductive lines;
- and
- a read circuit coupled to the plurality of conductive lines to generate the read data corresponding to the first data value or the second data value stored in a selected memory cell among the plurality of memory cells based on whether there is a change in a cell current flowing through the selected memory cell during a single read period,
- wherein, during the single read period, the read circuit generates the read data having the first data value responsive to the cell current having a constant level, and generates the read data having the second data value responsive to the cell current having an oscillating magnitude.
A memory device comprising:
- a memory cell array including a plurality of memory cells, each of the plurality of memory cells configured to store a data value corresponding to read data to be read out through a plurality of conductive lines;
- a sensing circuit coupled to the plurality of conductive lines to compare a cell current flowing through a selected memory cell among the plurality of memory cells with a reference current during a single read period;
- and
- a determination circuit coupled to the sensing circuit to:
- generate the read data having a first data value responsive to a comparison result of the sensing circuit indicating that the cell current has a constant level during the single read period;
- or generate the read data having a second data value responsive to a comparison result of the sensing circuit indicating that the cell current has an oscillating magnitude during the single read period.
An operating method of a memory device, comprising:
- setting a reference current to:
- a lower level than a distribution of cell currents flowing through memory cells that are in a low resistance state;
- or a higher level than the distribution of the cell currents flowing through memory cells that are in a high resistance state higher than the low resistance state;
- performing M comparison operations to compare a cell current flowing through a selected memory cell among the memory cells with the reference current, wherein M is an integer larger than 1;
- and
- generating read data having a second data value responsive to a comparison result indicating that the cell current has an oscillating magnitude.
Dependencies are inferred from the claim text.