Energy harvesting with dual buffer capacitor arrangement

A method of charging capacitors (16, 22) of a system (10), wherein the system comprises:

• an energy harvesting circuit (12) connectable to an antenna (14) and configured to execute an autonomous matching procedure to match the antenna (14) to an electric load (15);
• a buffer capacitor (16) connected to the energy harvesting circuit (14);
• a control circuit (20) connected to the energy harvesting circuit (14);
• an auxiliary capacitor (22) connectable to the energy harvesting circuit (14), the method comprising the steps of:
• charging the buffer capacitor (16);
• executing the autonomous matching procedure;
• and
• charging the auxiliary capacitor (22) during execution of the autonomous matching procedure,
• wherein the auxiliary capacitor (22) is charged by excess current provided by a voltage limiter (26) of the control circuit (20) during execution of the autonomous matching procedure.

A system (10) comprising:

• an energy harvesting circuit (12) connectable to an antenna (14) and configured to execute an autonomous matching procedure to match the antenna (14) to an electric load (15);
• a buffer capacitor (16) connected to the energy harvesting circuit (14) and chargeable by the energy harvesting circuit (14);
• a control circuit (20) connected to the energy harvesting circuit (14) and to the buffer capacitor (16) and connectable to the electric load (15), wherein the control circuit (20) is configured to control a supply voltage of the electric load (15);
• and
• wherein the control circuit (20) comprises an auxiliary capacitor (22) chargeable during execution of the autonomous matching procedure,
• the control circuit (20) comprises a voltage limiter (26) connected to an output of the energy harvesting circuit (14), and
• at least one of (A), (B), and (C) of which:
• (A) comprises:
• the voltage limiter (26) is connected to the auxiliary capacitor (22) and is operable to charge the auxiliary capacitor (22) when the control circuit (20) is in the antenna matching mode,
• (B) comprises:
• the voltage limiter (26) comprises a shunt limiter (27) operable to shunt excess current to ground, and
• (C) comprises:
• the control circuit (20) is either operable in an antenna matching mode or in a function mode and wherein the control circuit (20) is switchable from the antenna matching mode into the function mode upon or after completion of the autonomous matching procedure,
• the control circuit (20) comprises a switching arrangement (24) operable to switch the control circuit (20) between the antenna matching mode and the function mode, and
• the switching arrangement (24) comprises a PMOS transistor (PM3) and an NMOS transistor (NM3) and wherein a gate of the PMOS transistor (PM3) is connected to a gate of the NMOS transistor (NM3) and is connected to a switch input (34) providing a control signal being indicative of one of the antenna matching mode and the function mode.