Processor with in-band fault-injection detection in the presence of exceptions
AssigneeNovoton Technology Corporation
InventorZiv Hershman
Life of this patent
Estimating the term…
Abstract
An apparatus for protecting a processor includes an input interface and protection circuitry. The input interface is configured to monitor code instructions that are processed by the processor. One or more of the code instructions include one or more error-detection bits. The protection circuitry is configured to detect one or more errors in the program code using the error-detection bits, and to initiate responsive actions in response to detecting the errors, while accounting for exception events occurring in the processor.
Claims20
An apparatus for protecting a processor, the apparatus comprising:
- an input interface, configured to monitor code instructions that are processed by an instruction pipeline of the processor, one or more of which code instructions comprising one or more error-detection bits inserted at respective bit locations within the code instructions;
- and
- protection circuitry, configured to:
- detect one or more errors in the program code using the error-detection bits in the code instructions, and initiate responsive actions in response to detecting the errors, while accounting for exception events occurring in the processor;
- and
- cause the instruction pipeline to ignore the error-detection bits while processing the code instructions, by notifying the instruction pipeline of the bit locations of the error-detection bits.
A processor, comprising:
- an instruction pipeline, configured to fetch and execute program code comprising code instructions, one or more of which code instructions comprising one or more error-detection bits inserted at respective bit locations within the code instructions;
- and
- protection circuitry, configured to:
- monitor at least the error-detection bits in the code instructions, to detect one or more errors in the program code using the error-detection bits while accounting for exception events occurring in the processor, and to initiate a responsive action in response to detecting the errors;
- and
- cause the instruction pipeline to ignore the error-detection bits while processing the code instructions, by notifying the instruction pipeline of the bit locations of the error-detection bits.
A method for protecting a processor, the method comprising:
- monitoring code instructions that are processed by an instruction pipeline of the processor, one or more of which code instructions comprising one or more error-detection bits inserted at respective bit locations within the code instructions;
- detecting one or more errors in the program code using the error-detection bits in the code instructions, while accounting for exception events occurring in the processor;
- initiating a responsive action in response to detecting the errors;
- and
- causing the instruction pipeline to ignore the error-detection bits while processing the code instructions, by notifying the instruction pipeline of the bit locations of the error-detection bits.
Dependencies are inferred from the claim text.