Memory management

A computer-implemented method comprising:

• executing instructions in one of a plurality of execution states;
• and
• in response to a memory access request specifying a target virtual address corresponding to a target memory region to be accessed, translating the target virtual address into a target physical address, where a mapping from the target virtual address to the target physical address depends at least on a stage-1 address mapping specified for the target virtual address by a target stage-1 translation table entry in a stage-1 translation table structure, the stage-1 translation table structure being accessible using a stage-1 base address settable by an instruction executed by processing circuitry in a first execution state;
• in which:
• at least when the memory access request is a write request, the memory access request is rejected in response to determining that both of the following conditions are satisfied:
• stage-1 permission information specified by the target stage-1 translation table entry specifies that the target memory region is a guarded-control-stack (GCS) region for storing a GCS data structure for protecting return state information for returning from a function call or exception;
• and
• the memory access request is a request other than a GCS memory access request triggered by one of a restricted subset of GCS-accessing types of instruction;
• a translation hardening mechanism is supported for defining, based at least on translation hardening information settable by an instruction executed in a second execution state with greater privilege than the first execution state, at least one hardened stage-1 translation table entry which is protected by the translation hardening mechanism from being tampered with by an instruction executed in the first execution state;
• and
• the method comprises:
• when an anti-aliasing property is specified for the target memory region, rejecting the memory access request in response to detecting that the target stage-1 translation table entry or another stage-1 translation table entry used to locate the target stage-1 translation table entry is an unhardened translation table entry which is unprotected by the translation hardening mechanism;
• and
• in at least one operating state of the processing circuitry, rejecting the memory access request in response to determining that the memory access request is said GCS memory access request and the anti-aliasing property is not specified for the target memory region.

A non-transitory storage medium storing a computer program comprising instructions which, when executed by a host data processing apparatus, control the host data processing apparatus to provide an instruction execution environment for executing target code, the computer program comprising:

• processing program logic to simulate execution of instructions of the target code in one of a plurality of execution states;
• and memory management program logic to translate, in response to a memory access request specifying a target virtual address corresponding to a target memory region to be accessed, the target virtual address into a simulated target physical address, where a mapping from the target virtual address to the simulated target physical address depends at least on a stage-1 address mapping specified for the target virtual address by a target stage-1 translation table entry in a stage-1 translation table structure, the stage-1 translation table structure being accessible using a stage-1 base address settable by an instruction simulated as being executed in a first execution state;
• in which:
• at least when the memory access request is a write request, the memory management program logic is configured to reject the memory access request in response to determining that both of the following conditions are satisfied:
• stage-1 permission information specified by the target stage-1 translation table entry specifies that the target memory region is a guarded-control-stack (GCS) region for storing a GCS data structure for protecting return state information for returning from a function call or exception;
• and the memory access request is a request other than a GCS memory access request triggered by one of a restricted subset of GCS-accessing types of instruction;
• the memory management program logic is configured to support a translation hardening mechanism for defining, based at least on translation hardening information settable by an instruction simulated as being executed in a second execution state with greater privilege than the first execution state, at least one hardened stage-1 translation table entry which is protected by the translation hardening mechanism from being tampered with by an instruction simulated as being executed in the first execution state;
• when an anti-aliasing property is specified for the target memory region, the memory management program logic is configured to reject the memory access request in response to detecting that the target stage-1 translation table entry or another stage-1 translation table entry used to locate the target stage-1 translation table entry is an unhardened translation table entry which is unprotected by the translation hardening mechanism;
• and in at least one operating state of the processing program logic, the memory management program logic is configured to reject the memory access request in response to determining that the memory access request is said GCS memory access request and the anti-aliasing property is not specified for the target memory region.