Flushing cache lines involving persistent memory
AssigneeAltera Corporation
InventorsSharath Raghava, Nagabhushan Chitlur, Harsha Gupta
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Abstract
A method includes receiving, via a communication link and at a device of an integrated circuit system, a cache line comprising a destination address, determining, via the device, a type of memory or storage associated with the destination address, the type of memory or storage comprising persistent or non-persistent, and tagging the cache line with metadata in a manner indicating the type of memory or storage associated with the destination address.
Claims20
A method comprising:
- receiving, via a coherent link and at a device of an integrated circuit system, a cache line comprising a destination address, wherein the coherent link includes coherent link soft logic in the device;
- determining, via the coherent link soft logic of the device, a type of memory or storage associated with the destination address as persistent or non-persistent;
- and
- tagging, via the coherent link soft logic of the device, the cache line with metadata in a manner indicating the type of memory or storage associated with the destination address, wherein the coherent link soft logic comprises a decoder configured to decode the cache line to determine a destination of the cache line.
An integrated circuit system comprising:
- a central processing unit;
- a device comprising:
- a memory controller configured to manage memory coupled to the device;
- and
- a decoder configured to decode a cache line to determine a destination of the cache line;
- a communication link coupling the device to the central processing unit;
- a volatile memory coupled to the device;
- and
- a persistent memory coupled to the device;
- wherein the integrated circuit system is configured to:
- receive, via a coherent link and at the device of the integrated circuit system, the cache line, wherein the coherent link includes coherent link soft logic in the device;
- identify, via the coherent link soft logic of the device, whether the cache line is directed to the persistent memory or the volatile memory;
- and
- tag, via the coherent link soft logic of the device, the cache line with metadata to distinguish cache lines directed to the persistent memory from cache lines directed to the volatile memory, wherein the coherent link soft logic of the device comprises the decoder configured to decode the cache line to determine the destination of the cache line.
A non-transitory, tangible, and computer-readable medium comprising instructions that, when executed by a processor of a memory controller, cause the memory controller to perform operations comprising:
- receiving, via a coherent link and at a device of an integrated circuit system, a cache line into a queue configured to store pending operations, wherein the coherent link includes coherent link soft logic in the device;
- determining, via the coherent link soft logic of the device, if the cache line is directed to persistent memory or non-persistent memory based upon whether the cache line is tagged with metadata, wherein the coherent link soft logic of the device comprises a decoder configured to decode the cache line to determine a destination of the cache line;
- identifying a power failure;
- and
- in response to identifying the power failure:
- committing the cache line to memory in response to the cache line being directed to the persistent memory;
- and
- refraining from committing the cache line to memory in response to the cache line being directed to the non-persistent memory.
Dependencies are inferred from the claim text.