Supporting multiple vector lengths with configurable vector register file

A non-transitory computer readable medium comprising a circuit representation that, when processed by a computer, is used to program or manufacture an integrated circuit comprising:

• a data store configured to store a vector length parameter;
• a processor core including:
• a vector register;
• a vector execution unit comprising an operand buffer, wherein the vector register and the operand buffer have a same length in bits;
• and
• one or more multiplexors configured to selectively route data of a first architectural register stored in a first portion of the vector register to one of multiple disjoint portions of the operand buffer based on an identity of a second architectural register providing a second operand for an instruction being executed;
• wherein the processor core is configured to:
• while a first value of the vector length parameter is stored in the data store, store a single architectural register of an instruction set architecture in the vector register;
• and
• while a second value of the vector length parameter is stored in the data store, store multiple architectural registers of the instruction set architecture in respective disjoint portions of the vector register.